82C836 Datasheet, PDF (39/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s Bus Control Arbitration and Basic Timing
Clock/Bus Control
performs the refresh then returns control to the Master following deassertion of
-XMEMR. HOLD and HLDA remain asserted continuously throughout all Master
cycles, including Master initiated refresh.
The 82C836 incorporates a state machine that generates I/O channel bus cycles for all
CPU cycles not claimed by the internal memory address decode logic. The state machine
synthesizes the address strobe signal (ALE), the bus command signals (-XIOR, -XIOW,
-XMEMR, and -XMEMW), and MODA0 and MODA20. It monitors the state of the
-IOCS16 and -MEMCS16 signals to determine if the device on the bus is capable of
16-bit operations for I/O and memory, respectively. If a 16-bit operation is attempted
with an 8-bit device, the 82C836 performs conversions of 16-bit CPU operations to
paired 8-bit AT bus cycles.
The 82C836 supports XD-bus peripherals. Internal configuration register 44H controls
the SDIRH and SDIRL signals for different peripherals. 16-bit X-bus resources (other
than ROM) must generate -MEMCS16 and/or -IOCS16 just as any 16-bit add-on card
would.
The 82C836 itself asserts -MEMCS16 and/or -IOCS16 as follows:
• The 82C836 asserts -MEMCS16 during CPU, DMA or Master accesses to ROM if it
is 16-bits wide, and during CPU, DMA or Master accesses to local DRAM.
• The 82C836 asserts -IOCS16 during accesses to EMS I/O ports 2x8H and 2x9H
(x = 0 or 1, programmable), which operate as a 16-bit I/O resource.
• Although the coprocessor operates as a 16-bit I/O resource in most respects, the
82C836 does not assert -IOCS16 during coprocessor accesses.
The CPU local bus and the AT bus are tightly coupled. Activity on either bus directly
corresponds to similar activity on the other bus (the AT bus, however, remains idle
during certain CPU local bus operations). The general start/end protocol for each bus
cycle is as follows:
• On the CPU local bus, the start of a CPU controlled bus cycle is indicated by the
low-to-high transition of -ADS, and the end of the cycle is indicated by -READY
being active at the end of a subsequent T-state. The T-state, in which -ADS goes high,
is equivalent to an 80286 TS state. This is true for either pipelined or nonpipelined
80386sx cycles. An 80386sx T1-T2-T2 sequence is equivalent to an 80286 TI-TS-TC
sequence (TI = idle state). Virtually no useful work can be performed by the 82C836
during a T1 state because the CPU address and status signals are not guaranteed to be
valid until after the middle of T1. An 80386sx T1P-T2P sequence is equivalent to an
80286 TS-TC sequence, and useful work can be started during T1P.
• On the AT bus, the start of a CPU generated bus cycle is indicated by an ALE pulse,
followed by an I/O or memory command signal going active (low). The end of the
cycle is indicated by the command signal going inactive. The unlatched address
(UA17-23) must be valid before the end of the ALE pulse; and remains valid for a
short hold time after the start of command. The latched address (SA0-19) must be
valid before the start of command; and must remain valid for a short hold time after
the end of command. Read data must be valid before the end of the command pulse;
and must remain valid for a short hold time after the end of command. Write data
4-4 Revision 3.0
PRELIMINARY
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