82C836 Datasheet, PDF (162/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s CPU Access to AT-Bus
System Timing Relationships
Hidden Refresh (PROCCLK-Based, No HLDA)
Figure 11-17 shows hidden refresh timing. In hidden refresh, the CPU is allowed to
continue operating during refresh cycles. HOLD and HLDA are not used. Obviously,
the CPU cannot be allowed to access local memory or the AT bus during refresh. So,
the main usefulness of hidden refresh is in cache based systems to allow cache read hits
to continue during refresh. The basic protocol for hidden refresh is as follows:
• If a CPU cycle is already in progress when the 82C836 needs to perform a refresh
cycle, the 82C836 waits for the CPU cycle to end (indicated by -READY). If no CPU
cycle is in progress (-READY has occurred but no new -ADS yet), the hidden refresh
cycle can begin immediately.
• The 82C836B asserts ALE throughout the hidden refresh cycle.
• Two PROCCLK cycles after ALE goes high, -REF and -LOMEGCS go low. -CAS
goes low on the same PROCCLK edge as -REF. The delay from ALE to -REF allows
time for CAS precharge when using CAS-before-RAS refresh.
• After additional delay, -XMEMR and -RAS go low for a few PROCCLKs, then back
high. The 82C836 provides the refresh address for the DRAMs using MA0-10, but
other external logic must provide the refresh address for the AT bus.
• As in HLDA based CAS-before-RAS refresh cycles, -MWE goes high while -CAS
is low.
• A few PROCCLKs after the end of -XMEMR, -REF goes high.
• Finally, after further delay, ALE goes low. If the CPU attempted to start a local
memory or AT bus access during the hidden refresh cycle, CPU wait states are
inserted as needed to allow the refresh to complete. When ALE goes low, the waiting
CPU cycle is allowed to proceed. The T1 state for the waiting CPU can overlap the
hidden refresh cycle, but the normal T2 states begin after ALE goes low. For
example, Figure 11-17 shows a local memory write being delayed until the end of the
hidden refresh. -RAS goes low for the memory write in the middle of the first T-state
after the end of the hidden refresh.
Since hidden refresh is useful only in cache-based systems, which must use nonpipeline
mode, hidden refresh is designed to work in nonpipeline mode only.
-MWE needs to go high during CAS-before-RAS refresh to prevent the DRAMs from
going into Test mode. This is incompatible with the use of MD buffers if -MWE is used
as the direction control for the buffers; a high logic level on -MWE would cause the MD
buffers to drive the CPU local data bus, interfering with cache read hit activity. Thus, in
a cache-based system using hidden refresh, MD buffers should not be used. Worst case
system timing and loading analysis shows that MD buffers aren’t needed in any case, in
any cache or non-cache configuration; worst-case system timing margins are better
without MD buffers.
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