82C836 Datasheet, PDF (86/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s Programming the Interrupt Controller
Interrupt Controller
Figure 7-8. ICW2----Address 021H (0A1H) Write Only
B7 B6 B5 B4 B3 B2 B1 B0
______________________________________________ ___________________________
X
V<7:3> Interrupt Vector
bits: B0-B2 X
B3-B7 V<7:3>
These bits are ignored.
These bits are the upper five bits of the interrupt vector and are
programmable by the CPU. The lower three bits of the vector are
generated by the Priorty Resolver during INTA. INTC1 and INTC2
need not be programmed with the same value in ICW2.
Figure 7-9. ICW3 Format for INTC1----Address 021H Write Only
B7 B6 B5 B4 B3 B2 B1 B0
__________________________________________________________________________
S<7:0> Slave Mode
bits: B0-B7 S<7:0> Select which IR inputs have Slave mode controllers connected.
ICW3 in INTC1 must be written with 04H for INTC2 to function.
Figure 7-10. ICW3 Format for INTC2----Address 0A1H Write Only
B7 B6 B5 B4 B3 B2 B1 B0
______________________________________________ ___________________________
ID<2:0> Identify Slave Mode Address
0
bits: B0-B2
B3-B7
ID<2:0>
0
Determine the Slave Mode address the controllers will respond to
during the cascaded INTA sequence. ICW3 in INTC2 should be
written with 02H for cascade Mode operation. Note that B3-B7
should be zero.
These bits are zeros.
7-1 0 Revision 3.0
PRELIMINARY
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