82C836 Datasheet, PDF (138/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s CPU Access to AT-Bus
System Timing Relationships
CPU accesses to the AT bus, whether memory or I/O, read or write, can be ‘‘claimed’’
by external logic using the Early READY or LBA modes. If either of these modes is
enabled, but an AT bus access is not claimed by external logic, the 82C836 will perform
a normal AT bus cycle as shown in the diagram, except for one minor timing difference:
one additional PROCCLK cycle is inserted in the delay from mid-TS to ALE. In effect,
the 82C836 waits unit the end of TS insead of the middle to decide whether or not it
should perform an AT bus cycle.
SDIRL and SDIRH typically are either both low or both high. During DMA or Master
cycles, however, byte swapping may require one of these signals to be low while the
other remains high. The default state during bus idle periods is both signals high.
-8042CS and -RTCCS (MFP5 with external RTC), if asserted, follow -LOMEGCS
timing; namely, they are updated at the start of each TS and remain latched until the next
TS state or HLDA assertion.
Interrupt Acknowledge cycles are treated as I/O reads from an 8-bit resouce, except that
ALE and command are not generated, and the read data is an interrupt vector number
originating from the interrupt controller section of the 82C836.
Halt cycles result in assertion of -READY, but no command is generated on the AT bus.
Shutdown cycles result in the assertion of both -READY and CPURST. Shutdown is
used intentionally by some software programs, especially on 80286-based systems, to
trigger a CPU reset and thereby bring the CPU out of protected mode. CPU reset doesn’t
necessarily result in system reboot; in AT-compatible architectures, certain designated
locations in CMOS RAM are used by the BIOS to determine how the BIOS will respond
to the CPU reset. The BIOS can be instructed to return control to a resident real mode
program rather than reboot the operating system.
Other than shutdown, the conditions causing the 82C836 to reset the CPU include:
• Fast CPU reset via port 92H (PS/2 compatible).
• CPU reset via the 8042 keyboard controller (AT-compatible).
• Hardware system reset via PWRGOOD (also causes XRST).
Memory write operations to an area programmed as EPROM (-ROMCS) result in write
cycles on the AT bus. -XMEMW is generated. -ROMCS remains inactive (high) during
write operations.
Memory writes to write-protected shadow RAM go nowhere i.e., normal DRAM write
timing is followed except -CAS is suppressed. No cycle is generated on the AT bus.
-MEMCS16 and -IOCS16 Timing
Figure 11-4 describes the timing relationships for -MEMCS16 and -IOCS16. In most
AT-compatible architectures, -MEMCS16 will be an unlatched decode of the high-order
unlatched address bits, UA17-23. Similary, -IOCS16 will be an unlatched decode of the
latched address bits, SA0-19 (possibly gated with the I/O command signal).
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