82C836 Datasheet, PDF (91/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

Section 8
DMA Controller
Memory Refresh and DMA functions are implemented within the 82C836 as independent
bus masters, i.e., the refresh controller is separate from the 8237-compatible DMA
controllers. The 82C836 arbitrates refresh and DMA functions with internal logic and
gains control of the local bus via the HOLD/HLDA protocol of the 80386sx.
The 82C836 contains two DMA controllers compatible with the Intel 8237. Each
controller is a four-channel DMA device that can generate the memory addresses and
control signals necessary to transfer information directly between a peripheral device and
memory. This allows efficient information transfer with little CPU intervention and a
minimum of bus overhead.
The two DMA controllers are internally cascaded to provide four DMA channels for
transfers to 8-bit peripherals (DMA1), and three channels for transfers to 16-bit
peripherals (DMA2). DMA2, channel 0, provides the cascade interconnetion for the
two DMA devices, thereby maintaining IBM PC/AT compatibility.
Figure 8-1 shows how the two controllers are cascaded. DMA channels 0-3 are used for
8-bit transfers, while channels 5-7 are used for 16-bit transfers. DMA operations are
allowed within the full range of 16MB memory through the use of DMA page registers.
Figure 8-1. Cascaded DMA Controllers
Chips and Technologies, Inc.
PRELIMINARY
Revision 3.0 8-1