82C836 Datasheet, PDF (136/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s CPU Access to AT-Bus
System Timing Relationships
For the 82C836, the first useful T-state of each CPU cycle is either T1P, or the first T2
after T1 (i.e., the T-state in which -ADS changes from low to high). This T-state is
referred to as ‘‘TS’’ (T-start) and is directly equivalent to the TS state in 80286-based
systems. The delay from the middle of TS to the rising edge of ALE is variable,
depending on the phase and frequency relationship of BUSCLK to PROCCLK.
Although BUSCLK is derived from (and therefore synchronous with) PROCCLK, the
exact phase can still vary from one bus cycle to the next, especially if BUSCLK =
PROCCLK/5 or PROCCLK/6. The minimum delay from mid-TS to ALE rise is as
follows:
• 1.0 cycle of PROCCLK if BUSCLK = CXIN/4
• 1.5 cycles of PROCCLK if BUSCLK = CXIN/5
• 2.0 cycles of PROCCLK if BUSCLK = CXIN/6
The minimum delay from command rise to -READY fall is one cycle of PROCCLK in
all cases. -READY, in turn, is always synchronized to the last T2 or T2P of the bus cycle.
Bus conversion always begin with MODA0 forced low for the first AT bus cycle, then
forced high for the second cycle. This is true for the Force Bus Convert mode as well as
normal bus conversions.
Normal bus conversion occurs on any CPU-generated memory or I/O read or write in
which the CPU is requesting 16 bits of data to or from an 8-bit resource at an even
memory or I/O address. (If the address is odd, the CPU itself automatically performs two
separate byte transfers for a word operand.)
If no bus conversion is needed (i.e., only a single AT bus cycle is needed), there will be
only one command pulse. End-of-cycle timing then begins at the end of the first
command pulse instead of the second one. MODA0 tracks CPU A0 (-BLE), but is still
latched during each TS (transparent during the first half of TS).
CPU operation during AT bus cycle is always nonpipelined, as shown in Figure 11-3, if
the -NA output from the 82C836 is connected to the -NA input on the CPU. However,
the 82C836 -NA signal can be used for other purposes; and the CPU -NA input can be
tied low or high, or controlled by other external logic. In such cases, it is possible for the
CPU to operate in pipelined mode during an AT bus cycle, resulting in the following
changes in the timing relationships:
• The last state of the cycle can be a T2P instead of T2, in which case the next T-state
will be T1P, with a new CPU cycle starting immediately (if the final state is T2, then
the earliest that a new cycle can start is the first T2 after T1).
• -NA timing is affected as shown in Figure 11-3.
• CPU address no longer remains valid throughout the cycle, so it must be latched
externally in order to meet SA-bus requirements. If 74F543 latches are used, -NA
from the 82C836 can be used as a latch enable (a 74F244 and 74F373 can be used
instead of a 74F543 if desired).
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