82C836 Datasheet, PDF (176/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s AC Characteristics 16- and 20MHz
System Characteristics
DMA Access to AT-Bus, On-board I/O, and ROM
Tables 12-12 through 12-14 are the specification requirements for DMA to access the
AT-bus, on-board I/O, and ROM.
Table 12-12. DMA to AT-Bus, On-board I/O, and ROM----Output Responses
Symbol
t190
t191
t192
t194
t195
t197
t198
t199
t200
t201
t202
t203
Parameters
-DACKn or -DACKEN delay from BUSCLK rise
ALE rise from HLDA rise
DMA Address delay from BUSCLK rise
Command fall from BUSCLK rise
Command rise from BUSCLK rise
TC rise from BUSCLK rise
TC fall from BUSCLK rise
LOMEGCS delay from A16-23
Hold delay from PROCCLK rise at start of T-state
DSELA, B delay from OSC2 rise in MRA mode
DACKA, B, C valid before DACKEN fall in MRA
mode
DACKA, B, C hold after DACKEN rise in MRA
mode
Note: DMA address refers to A0-23, MODA0, MODA20, and -BHE.
16MHz
Min. Max.
---- 50
---- 75
---- 40
---- 45
---- 45
---- 40
---- 40
---- 35
5
36
---- 35
0
----
0
----
20MHz
Min. Max.
---- 50
---- 70
---- 35
---- 40
---- 40
---- 40
---- 35
---- 35
5
33
---- 35
0
----
0
----
Table 12-13. DMA to AT-Bus, On-board I/O, and ROM----Formula Specifications
Symbol
te194
te195
Critical Path
Command low time
Command high time
Formula
t194-t195
t195-t194
16MHz
Min. Max.
---- 10
---- 10
20MHz
Min. Max.
---- 10
---- 10
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