82C836 Datasheet, PDF (141/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

System Timing Relationships
CPU Access to AT-Bus s
-NA/-STCYC Timing
Figure 11-3 shown earlier identifies all possible timing relationships for the
-NA/-STCYC output from the 82C836. If -NA mode has been selected (via the
-DACK3 strap option), the default state of -NA during idle periods is low. -NA is
sampled by the CPU at the middle of T2 or T1P.
If the 82C836 -NA output is connected to the CPU -NA input and -NA is high during a
bus cycle, the CPU will operate in nonpipelined mode during the cycle, and the cycle
ends with a T2 state, not T2P. -NA always goes low at the end of the final T2 of each
cycle. It goes high again if needed as the start of the next T2 after T1.
If -NA stays low during a cycle, it will go high if needed at the start of the next TS (T1P
or first T2 after T1).
If the 82C836 -NA output is not connected to the CPU -NA input, then it is possible for
the CPU to remain in pipelined mode even though the 82C836 -NA output is high. In
this case, -NA still goes low at the end of the final T2P, but it may go high again at the
middle of the following T1P. Thus, there is a guaranteed low time of one PROCCLK on
the 82C836 -NA output, which allows it to remain usable as an address latch enable
signal (-ADRL).
If the -STCYC mode is selected instead of -NA, then the CPU -NA input must be tied
high or low or controlled externally, and external latches (74F543 or equivalent) must
be used between the CPU address bus and -SA bus. As shown in the diagram, -STCYC
goes low during the first half of each TS, thereby signalling external devices that a bus
cycle is starting. This timing also allows -STCYC to function as an address latch enable
for the A0-23 to -SA bus latches.
The -NA/-STCYC output is forced low when HLDA is high. This is redundant in the
-NA mode, since -NA is low between CPU bus cycles in any case. In -STCYC mode,
forcing -STCYC low causes the -SA bus address latches (if used) to become transparent
while HLDA is asserted, thereby allowing DMA and refresh addresses to pass through
(master addresses flow through in the opposite direction and are not latched by -ADRL.
In -NA mode, the -NA output operates as a ‘‘local memory hit ’’ indicator. Low on -NA at
mid-TS indicates that the 82C836 has detected a CPU read or write to local DRAM. In
all other cases, -NA is high at mid-TS. Depending on CPU address delay and the exact
address decoding path taken through the 82C836, it is possible for -NA to glitch
momentarily at the start of TS if -NA was low during the preceeding bus cycle. As long
as CPU address delay is within CPU specifications, -NA will be stable and valid by the
middle of TS, where the CPU samples it.
The duty cycle of -ADS provides a quick indication of whether or not the CPU is
operating in pipeline mode. If -ADS goes back low at any time during a bus cycle before
the end of -READY, the CPU has entered the pipeline state (T2P) and the next T-state
after READY will always be T1P, never T1 or TH. On the other hand, if -ADS is still
high when -READY is asserted, the next T-state after READY will be T1, TI or TH, but
never T1P. If a bus cycle ends in a nonpipelined state (T2), the only way the CPU can
get back into the pipeline state (T2P) is to go through T1 and at least one T2 first.
-NA/-STCYC operation and timing are unaffected by ‘‘cycle claiming ’’ in the Early
READY or LBA modes. The state of -NA at mid-TS still indicates whether or not the
82C836 detected a CPU memory access at an address that resides in local DRAM.
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