82C836 Datasheet, PDF (43/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s DRAM Interface
System Interface
RAM that can be accessed instead of ROM in the 0C0000H-0FFFFFH range is called
shadow RAM. (RAM in the 0A0000H-0BFFFFH range is also referred to as shadow
RAM.) This feature is invoked by copying an image of the BIOS (which is in ROM)
into an area of RAM, thus allowing operating systems and software applications to make
faster accesses to the shadowed BIOS (rather than ROM which is much slower).
The degree of performance improvement derived from the use of shadow RAM depends
primarily on the difference in access times between ROM and DRAM cycles. At higher
system speeds, the difference can be significant. Additionally, shadow RAM maintains
maximum BIOS performance when using either a single 8-bit ROM (such as a 27512) or
two smaller 8-bit ROMs (for the same total ROM capacity). Using only one ROM
reduces component count and circuit board size.
The following procedure enables shadow RAM. The program that performs this
procedure must reside in RAM while it is executing, because ROM must be disabled
while writing to the shadow RAM area:
1. Disable interrupts.
2. Copy the ROM BIOS into RAM, below the start of ROM.
3. Disable -ROMCS using internal configuration register 48H.
4. Enable the shadow RAM using internal configuration registers 4AH-4CH.
5. Copy the BIOS from low DRAM into the area of memory allocated for shadow RAM.
6. If desired, the BIOS can be copied in several blocks by enabling -ROMCS or shadow
RAM as needed and repeating steps 2 through 5 for each block.
7. Make the shadow RAM read-only, using internal configuration register 49H.
8. Re-enable interrupts.
DRAM Interface
The 82C836B includes a DRAM controller that directly supports up to 16MB of memory
in four banks. The DRAM controller in the 82C836B is capable of operating in three
possible modes:
• Multiple RAS Active (MRA), also known as dedicated CAS
In this mode, SCATsx provides four RAS signals and eight CAS signals for
controlling up to four DRAM banks, each bank 16-bits wide (plus two parity bits,
if desired). Each CAS signal is dedicated to controlling one eight-bit half of one
bank. Page interleaved access is used whenever possible, with up to four RAS
signals allowed to be active at the same time. The result is very high performance
in four-bank systems, since a high percentage of DRAM accesses can be CAS-only
zero wait-state accesses. MRA mode is recommended for all new designs, both for
performance reasons and to improve worst-case timing margins, particularly at
25MHz. The only disadvantage is that an external 74F153 and 74ALS138 are
needed to provide seven DREQ and DACK signals, see Figure 5-1.
5-2 Revision 3.0
PRELIMINARY
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