82C836 Datasheet, PDF (117/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

82C386 CHIPSet Data Sheet
Configuration Registers s
Table 10-6. Index 46H----Power Management (continued)
Bit
Name
6
Aux Parity
Disable
5
High Shadow
RAM Enable
Description
This bit, when set, is an alternate parity error clear and disable; in addition to
port 61H bit 2. Either this bit (if set), or port 61H bit 2 (if set), will clear the
internal parity error latch and prevent further parity error detection.
0 = Enable parity checking (default).
Port 61H bit 2 must also be zero to enable parity checking.
1 = Parity error clear and disable, independent of port 61H bit 2.
This bit causes memory accesses in the ‘‘High ROM ’’ area (see ICR 4EH,
bit 4) to be remapped into shadow RAM at the address obtained by forcing
A23-20 to 0H. This feature is useful in laptops in which shadow RAM is
used for BIOS, and it is desired to have CPU instruction fetches following
CPU reset go to 0FFFF0H in the shadowed BIOS area instead of going to
ROM at FFFFF0H (CPU reset without XRST is generally used to return to
real mode from protected mode). Do not set this bit unless shadow RAM
has been enabled in the translated address range. SCATsx will not perform
a ROM or AT bus access in response to a translated high ROM read or write,
regardless of other ICR bit settings. Shadow RAM write protection, if
enabled, applies to translated high ROM writes as well as other types of
writes. EMS has no effect on the translation, even if the translated address
happens to fall within the internal EMS page frame; the high ROM
translation bypasses the EMS mechanism. An Early Wait State always
occurs on translated high ROM accesses. Master accesses to high ROM are
affected by this bit in the same way as CPU accesses.
0 = No high ROM translation (default)
1 = Enable high ROM translation to shadow RAM
4
----
3-2
Run Freq
1-0
Sleep Freq
This bit is always cleared by a logic low level on PWRGOOD, even if
stand-by mode is enabled (see ICR 60H). Consequently, this bit cannot
affect high ROM accesses immediately following system reset via
PWRGOOD.
Reserved.
These bits select the frequency of the PROCCLK signal to the CPU when in
normal run mode.
00 = CXIN (default)
01 = CXIN/2
10 = CXIN/4
11 = CXIN/8
These bits select the frequency of the PROCCLK signal to the CPU when in
sleep mode.
00 = Stopped (default). See ICR 64H bits 4-3.
01 = CXIN/2
10 = CXIN/4
11 = CXIN/8
Note: Refresh, DMA and Master cycles always run at full speed, PROCCLK = CXIN, regardless of bits 3 -0.
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