82C836 Datasheet, PDF (150/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s CPU Access to AT-Bus
System Timing Relationships
Early READY and LBA Modes
Figure 11-10 shows how external logic can claim a CPU generated cycle by asserting
-LBA (0WS pin) or -READY during the first T2. In both cases, the 82C836 is prevented
from generating a local memory or AT bus cycle. For a read, the external logic (typically
a local cache) must provide the read data and generate -READY. The 82C836 is
responsive to early -READY or -LBA only if one or both of these modes has been
enabled by Internal Configuration register 41H.
Figure 11-10. Early READY and -LBA
Any CPU generated cycle, except a local memory write, can be claimed in this fashion,
including interrupt acknowledge cycles. Local memory writes normally cannot be
claimed by external logic and do not cause an early wait state. However, even local
memory writes can be claimed (and there will be an early wait state) if ICR 63H bit 0 is
set to one.
When these cycle claiming capabilities are used, the CPU must run in nonpipelined mode
only; the CPU -NA input must be tied high. This is necessary because of CPU address
timing. If the cycle is not claimed, then the 82C836 may need to generate a local
memory cycle. The 82C836 needs a valid CPU address in order to do this, but in
pipeline mode the CPU address may become invalid too soon for the 82C836.
Whenever the 82C836 finishes driving -READY during any cycle, it continues to drive
-READY actively high for one PROCCLK cycle. Then -READY is tri-stated, and an
external pull-up resistor keeps it high. The tri-stating of -READY cannot occur later than
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