82C836 Datasheet, PDF (85/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

Interrupt Controller
Programming the Interrupt Controller s
Figure 7-7. ICW1----Address 020H (0A0H) Write Only
B7 B6 B5 B4 B3 B2 B1 B0
___________________________ ________ ________ ________ ________ ________
X
SM
X
LTM
SI
X
Single Mode
Level Triggered Mode
Sequence Initialization
bits: B0 X
B1 SM
B2 X
B3 LTM
B4 SI
B5-B7 X
This bit is ignored.
Bit 1 selects between Single mode and Cascade mode. Single mode
is used whenever only one interrupt controller (INTC1) is used and is
not recommended for this device. Cascade mode allows the two
interrupt controllers to be connected through IR2 of INTC1. INTC1
allows INTC2 to generate its own interrupt vectors if Cascade mode
is selected and the higest priority IR pending is from an INTC2
input. INTC1 and INTC2 must be programmed for Cascade mode
for both devices to operate.
This bit is ignored.
Bit 3 selects the level or edge triggered inputs to the IRR. If a
one is written to LTM, a high-level on the IRR input generates an
interrupt request. The IR must be active until the first INTA cycle is
started to generate the proper interrupt vector (an IR7 vector is
generated if the IRR input is de-asserted early), and the IR must be
removed prior to EOI to prevent a second interrupt from occuring.
Bit 4 indicates to the interrupt controller that an initialization
sequence is starting and must be a one to write ICW1.
These bits are ignored.
Chips and Technologies, Inc.
PRELIMINARY
Revision 3.0 7-9