82C836 Datasheet, PDF (127/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

82C386 CHIPSet Data Sheet
Configuration Registers s
Timing considerations also require all externally claimed cycles to have zero wait states.
For cycles claimed via early READY, as with the 82C835 cache controller, this will
always be the case automatically. Cycle claiming via -LBA is effectively unusable when
hidden refresh is enabled unless -READY is asserted on the same T-state as -LBA.
If HLDA is already active for a DMA or Master cycle, normal refresh cycles occur as
needed without waiting for HLDA to end. The refresh requests internally sent to the
hidden refresh logic are reduced accordingly. Also, during sleep mode, normal
HOLD/HLDA refresh is performed instead of hidden refresh.
Table 10-19. Index 64H----CAS Timing for DMA/Master
Bit
Name
Description
7
Respond
Determines whether or not the 82C836B will perform a normal cycle in
During Reset
response to CPU activity occurring while CPU reset is active. The CPU can
initiate one or more bus cycles after CPURST has been asserted. The
82C836B can either ignore these cycles or respond normally as if no CPU
reset is in progress.
0 = Ignore CPU cycles starting after CPURST goes active (default)
1 = Respond as usual to CPU cycles starting after CPURST goes active.
6-5
----
Reserved. Write as 0.
4-3
Stopped Clock
These bits select the exact phase within a T-state in which PROCCLK stops
Sleep Phase
during sleep mode when a sleep frequency of zero has been selected. This
will allow maximum flexibility with static CPUs. Zero-frequency sleep
mode should be used only with a static CPU.
00 = PROCCLK low, 1st half of T-state (default)
01 = PROCCLK low, 2nd half of T-state
10 = PROCCLK high, 1st half of T-state
11 = PROCCLK high, 2nd half of T-state
2-0
CAS delay for
These bits determine when CAS is asserted during DMA or Master write
DMA/Master Write cycles to local memory. CAS assertion during reads is not affected. The
minimum delay from valid column address to assertion of CAS is one
PROCCLK. Up to four additional PROCCLKs can be added, for a
maximum of five PROCCLKs total.
000 = No added delay
001 = 1 PROCCLK delay added
010 = 2 PROCCLKs delay added
011 = 3 PROCCLKs delay added (default)
100 = 4 PROCCLKs delay added
101 = Reserved
110 = Reserved
111 = Reserved
For 25MHz operation, 011 should be optimum.
For 20MHz operation, 010 should be optimum.
For 16MHz operation, 001 should be optimum.
The timing of CAS is most critical relative to valid write data and parity.
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