82C836 Datasheet, PDF (90/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s Programming the Interrupt Controller
Interrupt Controller
Figure 7-14. OCW3----Address 020H (0A0H) Write Only
B7 B6 B5 B4 B3 B2 B1 B0
________ ________ ________ ________ ________ ________ ________ ________
RIS Select between IRR and ISR
RR Read Register
PM Polled Mode
1
SI
Select Initialization Mode
SMM
ESMM
0
Special Mask Mode
Enable Set/Reset
Special Mask Mode
bits: B0
B1
B2
B3
B4
B5
B6
B7
RIS
RR
PM
1
SI
SMM
ESMM
0
This bit selects between the IRR and the ISR during status read
operations if RR = 1. IRR is selected if this bit is set to one. ISR is
selected if this bit is set to zero.
When the RR bit is one, reading the status port at address 020H
(0A0H) causes the contents of IRR or ISR (determined by RIS) to be
placed on XD<7:0>. Asserting PM forces RR reset.
Polled Mode is enabled by writing a one to bit 2 of OCW3 causing
the 82C836 to perform the equivalent of an INTA cycle during the
next I/O read operation to the controller. The byte read during this
cycle sets bit 7 if an interrupt is pending. If bit 7 of the byte is set,
the level of the highest pending request is encoded on bit 2-0. The
IRR remains frozen until the read cycle is completed, at which time
the PM bit is reset.
This bit is set to one.
See SI shown in OCW2.
If ESMM and SMM are both written with a one, the Special Mask
Mode is enabled. Writing a one to ESMM and a zero to SMM
disables Special Mask mode. During Special Mask mode, writing a
one to any bit position inhibits interrupts; a zero enables interrupts on
the associated channel by causing the Priority Resolver to ignore the
condition for the ISR.
Writing a one in this bit position enables the Set/Reset Special Mask
Mode function controlled by bit 5 (SMM). ESMM allows the other
functions in OCW3 to be accessed and manipulated without
affecting the Special Mask mode state.
This bit is set to zero.
7-1 4 Revision 3.0
PRELIMINARY
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