82C836 Datasheet, PDF (13/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s Architectural Overview
82C836 CHIPSet Introduction
The SCATsx basic system architecture is shown in Figure 1-1.
Figure 1-1. SCATsx Basic System Architecture
DRAM
CPU
80386sx
PAR
D8-D15
D0-D7
A0-A23,BHE-
ADS,M/IO,D/C,W/R
HLDA
NPU
80387sx
OPTIONAL
RAS,CAS,MA,MWE
SA0-SA19
SCATsx
82C836
EPROM
8042
XD8-XD15
XD0-XD7
SDIRH
SD8-SD15
SD0-SD7
SDIRL
MODA0,20
COMMAND
SPKR
CMD
*
A1-A19,A21-A23,BHE-
* ^{Inbound during Master Cycles only.}
SA0-SA19,SBHE-
UA17-UA23
*
AT BUS
Architectural Overview
The major address and data buses are described in Table 1-1. Various memory and I/O
‘‘resources’’ are accessible from these buses. I/O resources contained within the 82C836
include: Internal Configuration Registers (ICRs), two DMA controllers, two interrupt
controllers, a Real Time Clock (RTC) with CMOS RAM, timer registers and EMS page
registers.
1 -2 Revision 3.0
PRELIMINARY
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