82C836 Datasheet, PDF (64/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

Real Time Clock and Internal Timer Registers
Control and Status Registers s
B7 UIP
B4-B6 DV
Update In Progress flag is a status bit used to indicate when an
update cycle is about to take place. A one indicates an update cycle
is taking place or is imminent. UIP goes active (HIGH) 244 µs prior
to the start of an update cycle and remains active for an additional
2 ms while the update is taking place. The UIP bit is read only and is
not affected by RESET. Writing a one to the SET bit in Register B
inhibits any update cycle and then clears the UIP status bit.
These bits control the Divider Prescaler on the Real Time Clock.
While the 82C836 RTC can operate at frequencies higher than
32.768KHz, this is not recommended for battery-powered operation
due to the increased power consumption at these frequencies. OSCI
frequencies and modes are:
• 4.194304MHz in operate mode when DV2 = 0, DV1 = 0
and DV0 = 0
• 1.048576MHz in operate mode when DV2 = 0, DV1 = 0
and DV0 = 1
• 32.768KHz in operate mode when DV2 = 0, DV1 = 1
and DV0 = 0
The divider is reset when DV2 = 1 and DV1 = 1, regardless of DV0.
Figure 6-2. Register B----Address 0BH (Read Only)
B7 B6 B5 B4 B3 B2 B1 B0
________ ________ ________ ________ ________________ ________ ________
DSE
24/12
0
UIE
AIE
PIE
SET
Daylight Savings Enable
24-hour Mode
Update-ended Interrupt Enable
Alarm Interrupt Enable
Periodic Interrupt Enable
Update Cycle Enable
bits: B0
DSE
B1
24/12
B2-B3 0
The Real Time Clock can be instructed to handle daylight savings
time changes by setting this bit to a one. This enables two
exceptions to the normal time-keeping sequence to occur. Setting
this bit to zero disables the execution of these two exceptions.
The 24/12 control bit is used to establish the format of both the hours
and hours alarm bytes. If this bit is a one, the Real Time Clock
interprets and updates the information in these two bytes using the
24-hour mode. This bit can be read or written to by the CPU and is
not affected by RESET.
Read as zeros.
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