82C836 Datasheet, PDF (71/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s Programming the Counter Timer Controller
Real Time Clock and Internal Timer Registers
B4-B7 F<0:3> These four bits determine the command to be performed as shown
below.
F3
F2
F1
F0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
XX
MSB = Most Significant Byte
LSB = Least Significant Byte
X = Don’t care
Command
Latch Counter 0 (See Counter Latch Command)
Read/Write counter 0 LSB only
Read/Write counter 0 MSB only
Read/Write counter 0 LSB then MSB
Latch Counter 2 (See Counter Latch Command)
Read/Write counter 1 LSB only
Read/Write counter 1 MSB only
Read/Write counter 1 LSB then MSB
Latch Counter 2 (See Counter Latch Command)
Read/Write Counter 2 LSB only
Read/Write Counter 2 MSB only
Read/Write Counter 2 LSB then MSB
Read-Back command (see Counter Read-Back
Command)
Read/Write Counter Command
When writing to a counter, two convensions must be observed:
• Each counter’s Control Word must be written before the initial count is written.
• Writing the initial count must follow the format specified in the Control Word (least
significant byte only, most significant byte only; or least significant byte, then most
significant byte).
A new initial count can be written into the counter any time after programming without
rewriting the Control Word, as long as the programmed format is observed.
During Read/Write Counter Commands M<2:0> are defined as follows:
• Select Mode 0
• Select Mode 1
• Select Mode 2
• Select Mode 3
• Select Mode 4
• Select Mode 5
when M2 = 0 and M1 = 0 and M0 = 0
when M2 = 0 and M1 = 0 and M0 = 1
when M1 = 1 and M0 = 0 (M2 is ‘‘don’t care’’)
when M1 = 1 and M0 = 1 (M2 is ‘‘don’t care’’)
when M2 = 1 and M1 = 0 and M0 = 0
when M2 = 1 and M1 = 0 and M0 = 1
6-1 2 Revision 3.0
PRELIMINARY
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