82C836 Datasheet, PDF (104/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s DMA Register Descriptions
DMA Controller
B2 MB
B3-B7 X
Bit 2 sets or resets the request mask bit for the channel selected by
MS1 and MS0. Writing a one in this bit position sets the mask,
inhibiting external requests.
These bits are ignored.
Alternatively, all four mask bits can be programmed in one operation by writing to the
Write All Mask Bits address. The data format for this function and the Read All Mask
Bits function is shown in Figure 8-7.
Figure 8-7. Request Mask Register----Write All Mask Bits
B7 B6 B5 B4 B3 B2 B1 B0
____________________________________ ____________________________________
MB<3:0> Mask Bit
X
bits: MB<3:0>
B4-B7
Each bit position in the field represents the mask bit of a channel.
The mask bit number corresponds to the channel number associated
with the mask bit. All four mask bits are set following a RESET or
a Master Clear command. Individual channel mask bits are set as a
result of terminal count being reached, if Auto-Initialize is disabled.
The entire register can be cleared, enabling all four channels, be
performing a Clear Mask register operation.
These bits are ignored.
8-1 4 Revision 3.0
PRELIMINARY
Chips and Technologies, Inc.