82C836 Datasheet, PDF (15/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s Architectural Overview
82C836 CHIPSet Introduction
Bus Conversion----Whenever the CPU attempts to transfer a 16-bit even-address word
to or from an 8-bit resource, the 82C836 converts the 16-bit CPU cycle into two
consecutive 8-bit cycles. The CPU is delayed by means of wait states until both 8-bit
cycles have been completed. Bus conversion by the 82C836 can occur on either I/O or
memory cycles, but only on CPU initiated cycles, not on DMA or Master cycles.
The following summarizes all possible cycles types in a SCATsx AT-compatible
architecture.
• CPU initiated local cycles (no command on AT bus)
° ^{Local DRAM read or write}
° ^{Interrupt acknowledge}
° ^{Halt/Shutdown}
• CPU initiated AT bus cycles (command generated on AT bus)
° ^{On-board ROM read or write}
° ^{On-board I/O read or write}
° ^{AT bus memory read or write}
° ^{AT bus I/O read or write}
• DMA
° ^{Memory to I/O (simultaneous memory read and I/O write)}
° ^{I/O to memory (simultaneous I/O read and memory write)}
• Master
° ^{Memory read or write (may access on-board DRAM and ROM)}
° ^{I/O read or write}
• Refresh
° ^{Normal (system initiated)}
° ^{Master initiated}
• Additional variations on the above types
° ^{Resource: 8/16 bit, memory or I/O, on-board or AT bus}
° ^{Data transfer size: byte or word}
° ^{Address: even or odd, first 1MB or not}
° ^{Delay or speed-up via IOCHRDY or 0WS}
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