82C836 Datasheet, PDF (123/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

82C386 CHIPSet Data Sheet
Configuration Registers s
The purpose of Index 60H is to allow DRAM refresh to continue during power-down.
Consequently, bits 7-3 are preserved during power-down instead of cleared by
PWRGOOD. To initialize this ICR to its default value, a logic low level on the Power
Sense (MFP5) input is used while PWRGOOD is low.
Table 10-15. Index 60H----Laptop Features
Bit
Name
Description
7
CAS-Before-RAS 0 = RAS only refresh (default)
Refresh Enable
1 = CAS before RAS refresh
6
Stand-by Refresh This mode allows local DRAM refreshing to continue during power-down.
Enable (also known No refresh address is generated during power-down, so CAS-before-RAS
as Stand-by mode) refresh should be enabled and DRAMs that support CAS-before-RAS
refresh should be used. Stand-by refresh relies on the 32KHz input clock
(MFP4 pin), which isn’t available with external RTC (MFP4 becomes
IRQ8). Consequently, stand-by refresh cannot be used with external RTC.
0 = No refresh during power-down (default)
1 = Refresh continues during power-down
This bit, when set to one, has the following additional effects: ICR 4DH bits
4-0 (memory configuration) are preserved during power-down. ICR 4EH bit
6 (MRA enable) is preserved during power-down. DACK signals are no
longer sampled following PWRGOOD rise. PWRGOOD fall (powering
down) takes effect only after stand-by refresh is operational to maintain
refresh continuity. For assured recovery from potential lockup conditions
following initial power turn-on or software malfunction, the 82C836B
contains a built-in 32KHz based timeout and external RTC interlock to clear
this bit automatically under abnormal conditions. PWRGOOD can then take
effect in the normal manner without standby mode
5-4
Stand-by
Allows reduced power consumption for stand-by refresh during power-
Refresh Interval down via reduced DRAM refresh rate if compatible DRAMs are used.
The reduced refresh rate takes effect only during power-down and only
if stand-by refresh is enabled.
00 = 15µs (default; half cycle of 32.768KHz input clock)
01 = 61µs (2 cycles of 32.768KHz input clock)
10 = 122µs (4 cycles of 32.768KHz input clock)
11 = 244µs (8 cycles of 32.768KHz input clock)
3
Refresh Time Base Indicates whether or not the system has switched from stand-by refresh to
(Read Only)
normal. If stand-by mode is enabled, the system switches from 14.3MHz
refresh timing to 32KHz timing during power-down. When power comes
back up, the BIOS must reprogram Timer Channel 1 (see Section 6,
Programmable Interval Timer) to get refresh request running again. The
82C836 then switches back to 14.3MHz based refresh. BIOS should not
try to access DRAM until the switch back to 14.3MHz timing has occurred.
The switching of the refresh time base is done in a double-synchronized
manner to prevent any lost or aborted refresh cycles.
0 = 14.3MHz based refresh
1 = 32KHz based refresh
2-0
----
Reserved. Write as 0.
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