82C836 Datasheet, PDF (23/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s Signal Descriptions
Pin Assignments
Table 2-5. I/O Channel Interface Signals
Pin
60-61
63-76
136
135
Type
Bidirectional
Bidirectional
Output
Output
97
Input
124
Bidirectional
57
Output
79
Bidirectional
80
Bidirectional
77
Bidirectional
78
Bidirectional
131
Output
Name
XD0<0:1>
XD0<2:15>
SDIRH
SDIRL
-MASTER
-REFRESH
ALE
-XIOR
-XIOW
-XMEMR
-XMEMW
-LOMEGCS
Description
----
16-bit system data bus for on-board I/O, on-board
ROM and (via buffers) AT bus data.
----
Channel data bus controls are outputs that control the
direction of the data buffer between the XD-bus and
the SD-bus. When the signals are high (default), data
flows from XD to SD; when the signals are low, data
flows XD from SD.
Master is an active-low input from the I/O channel’s
16-bit extension. -MASTER allows a microprocessor,
or DMA controller, residing on the I/O channel to
control the system, address, data, and control lines.
Memory Refresh control is an active-low output to
the I/O channel that indicates a refresh cycle. During
Master cycles, -REFRESH is an input to the 82C836.
Address Latch Enable is an active-high output used to
latch valid addresses on the I/O channel. ALE is held
continuously high during Refresh, DMA, and Master
cycles.
I/O Read command is an active-low output used by
I/O devices to put their data on the bus. This signal
is used by on-board peripherals as well as the I/O
channel. During Master cycles, -XIOR is an input
command to the perpherals and the 82C836.
I/O Write command is an active-low output used by
I/O devices to capture data from the bus. This signal
is used by on-board peripherals as well as the I/O
channel. During Master cycles, -XIOW is an input
command to the peripherals and the 82C836.
Memory Read command is an active-low output used
by XD-bus, video memory, and I/O channel memory.
During Master cycles, -XMEMR is an input command
to the peripherals and the 82C836. During memory
refresh and DMA cycles, -XMEMR is always an
output.
Memory Write command is an active-low output
used by XD-bus, video memory, and I/O channel
memory. During Master cycles, -XMEMW is an
input command to the peripherals and the 82C836.
During memory refresh and DMA cycles, -XMEMW
is always an output.
Low Meg Chip Select is an active-low output that is a
decode of memory accesses below 1MB. This output
is used to gate -SMEMR and -SMEMW onto the AT
bus (8-bit section) from -XMEMR and -XMEMW,
respectively. -LOMEGCS operates in this manner
for DMA and Master cycles as well as CPU cycles.
2-6 Revision 3.0
PRELIMINARY
Chips and Technologies, Inc.