82C836 Datasheet, PDF (8/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s Contents
82C836 CHIPSet Data Sheet
Figure 8-5.
Figure 8-6.
Figure 8-7.
Figure 8-8.
Request Register Read Format . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13
Request Mask Register ----Write Single Mask Bit . . . . . . . . . . . . . 8-13
Request Mask Register ----Write All Mask Bits . . . . . . . . . . . . . . . 8-14
Status Register (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15
System Timing Relationships
Figure 11-1. CPU Access to AT-Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 11-2. -MEMCS16 and -IOCS16 Timing . . . . . . . . . . . . . . . . . . . . . . . .
Figure 11-3. -NA/-STCYC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 11-4. -MEMCS16 and -IOCS16 Timing . . . . . . . . . . . . . . . . . . . . . . . .
Figure 11-5. IOCHRDY and -0WS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 11-6. -CAS-Only DRAM Access by CPU . . . . . . . . . . . . . . . . . . . . . . .
Figure 11-7. Local DRAM Bank Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 11-8. Maximum Wait State Page Miss . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 11-9. Cache Mode Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 11-10. Early READY and -LBA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 11-11. Coprocessor Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 11-12. DMA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 11-13. DMA and Master Access to Local Memory . . . . . . . . . . . . . . . . .
Figure 11-14. DRQ/DACK Scanning in MRA Mode . . . . . . . . . . . . . . . . . . . . .
Figure 11-15. Master Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 11-16. Refresh Timing (HLDA/14MHz-Based) . . . . . . . . . . . . . . . . . . .
Figure 11-17. Hidden Refresh (PROCCLK-Based, No HLDA) . . . . . . . . . . . . .
Figure 11-18. Standby Refresh (32KHz-Based) . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 11-19. Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-2
11-3
11-5
11-7
11-8
11-11
11-13
11-15
11-17
11-18
11-19
11-21
11-23
11-25
11-26
11-29
11-31
11-33
11-34
Timing Diagrams
Figure 13-1. Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 13-2. CPU to Local Memory ----Output Responses and
Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 13-3. CPU AT-Bus, On-Board I/O and ROM ----Output Responses . . .
Figure 13-4. CPU to AT-Bus, On-Board I/O and ROM ----Input Requirements
Figure 13-5. DMA to AT-Bus, On-Board I/O, and ROM ----Output Responses
Figure 13-6. DMA to AT-Bus, On-Board I/O and ROM ----Input Requirements
Figure 13-7. DMA and AT-Bus Master Access to Local Memory ----
Output Responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 13-8. DMA and AT-Bus Master Access to Local Memory ----
Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 13-9. Refresh----Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 13-10. Refresh----Output Responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 13-11. Miscellaneous Parameters ----Output Responses . . . . . . . . . . . . . .
Figure 13-12. Miscellaneous Parameters ----Input Requirements . . . . . . . . . . . . .
Figure 13-13. Local Bus Access and Cache ----Output Responses . . . . . . . . . . . .
Figure 13-14. Local Bus Access and Cache ----Input Requirements . . . . . . . . . .
Figure 13-15. Standby Refresh ----Output Responses . . . . . . . . . . . . . . . . . . . . . .
13-1
13-2
13-3
13-4
13-5
13-6
13-6
13-7
13-7
13-8
13-9
13-10
13-10
13-11
13-11
Mechanical Specifications
Figure 14-1. Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
x Revision 3.0
PRELIMINARY
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