82C836 Datasheet, PDF (33/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

Functional Description
Standby Power Management and Laptop Support s
inputs during the time the system is powered down to prevent noise on the inactive pins
from causing increased ICC. This pin must therefore be active (high) for the remainder
of the device to operate properly when system power is applied.
As most AT-compatible architectures, the reset and power good functions normally
available separately on an MC146818 are combined in the 82C836. The PWRGOOD
input serves not only as a power down control pin, but also as a general hardware reset
input. It does not reset the Real Time Clock.
Another pin is provided to initialize the Real Time Clock (RTC) whenever system or
battery power is first applied to the 82C836. The PS/MFP5 pin does not alter the CMOS
RAM or Clock/Calendar contents, but it does initialize the necessary RTC control
register bits. Deassertion of Power Sense (PS) disables the generation of RTC interrupts
and sets a flag indicating that the contents of the real time clock may not be valid. A
recommended circuit for controlling the PS input is also shown in Figure 3-3 above (refer
to applicable Product Alerts for the 82C836A Circuit).
Testability
All unnecessary inputs are disabled while PWRGOOD is low. In addition, all outputs
except OSC2 are held in a high-impedance state. OSC2, the 14.3MHz output driver, is
driven to a continuously low logic level. For in-circuit manufacturing test, the PS input
should also be pulsed low momentarily while PWRGOOD is low to insure that the
82C836 is fully reset.
Standby Power Management and Laptop Support
The 82C836B includes the following features for stand-by power management in laptop
applications:
• When the system has been powered down except for SCATsx and DRAM, SCATsx
can automatically switch from normal 14.318MHz based DRAM refresh to 32KHz
based DRAM refresh. This allows the contents of DRAM to be preserved during
power-down. ICR 60H is used to enable or disable the stand-by refresh capability. If
the stand-by refresh capability is enabled, SCATsx automatically switches to stand-by
refresh in response to a logic low level on the PWRGOOD input.
• Stand-by refresh is designed to utilize the CAS-before-RAS mode. In this mode of
refresh, the refresh address is generated internally by the DRAM and is not provided
by the 82C836B. ICR 60H is used to enable or disable CAS-before-RAS refresh. If
the CAS-before-RAS refresh mode is enabled, it applies during normal powered-on
operation as well as during power down intervals.
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