82C836 Datasheet, PDF (135/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

System Timing Relationships
CPU Access to AT-Bus s
The delay from ALE to the start of command, and the width of the command, depend on
the type of cycle, as shown in the following Table.
Table 11-1. Delays From ALE to Start Command in BUSCLK Cycles
Cycle Type
Memory Access to 16-bit resource
I/O Access to 16-bit resource
Memory or I/O to 8-bit resource
ALE:CMD
0
0.5
0.5
CMD Width
2.0
1.5
4.5
Figure 11-1 depicts a command width of 2.5 cycles of BUSCLK and a CMD delay of 0.5
cycle, a combination that never actually occurs unless -0WS is asserted. If the CMD
delay is 0.5 cycle of BUSCLK, the default command width will always be either 1.5 or
4.5 cycles of BUSCLK. During bus conversions (which can occur only when accessing
an 8-bit resource), the command inactive delay between the two bus cycles is always 1.5
cycles of BUSCLK. It is the resource type (8-bit or 16-bit), not data transfer size, that
determines cycle timing. For example, an 8-bit access to a 16-bit resource (-MEMCS16
and/or -IOCS16 asserted) follows the 16-bit timing shown above. -MEMCS16 and
-IOCS16 timing is shown in Figure 11-2.
Figure 11-2. -MEMCS16 and -IOCS16 Timing
Chips and Technologies, Inc.
PRELIMINARY
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