82C836 Datasheet, PDF (40/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

Clock/Bus Control
Bus Control Arbitration and Basic Timing s
must be valid near the beginning of command; and must remain valid for a short hold
time after the end of command. The command active time can be lengthened by
deasserting IOCHRDY, or (in most cases) shortened by asserting 0WS.
• Master cycles on the AT bus follow the same protocol as CPU controlled cycles,
except ALE remains continuously active (high), and unlatched address timing follows
latched address timing. Address and command signals are controlled by the add-on
card bus master during Master cycles.
• DMA cycles on the AT bus follow the same basic protocol as Master cycles except
the 82C836 controls the address and command signals, and commands always occur
in pairs (I/O read and memory write, or memory read and I/O write).
The minimum CPU local bus cycle in pipelined mode is two T-states, which occurs most
often on CAS-only accesses to local memory (see Section 5, System Interface, subsection
titled ROM/Shadow RAM Interface). In nonpipelined mode, the corresponding minimum
is three T-states, which the 82C836 assures by appropriately controlling the timing of
READY. If READY is controlled externally, two T-state cycles in nonpipelined mode
are possible as follows:
• During coprocessor accesses in which the coprocessor generates -READYO soon
enough to end the cycle after only two T-states. This can occur only if the 82C836
has been programmed to let the coprocessor control ready during coprocessor
accesses, and if the coprocessor -READYO output has been properly interfaced to
CPU -READY as described in Section 5, System Interface, subsection titled Numeric
Coprocessor Interface.
• During external cache ‘‘hit’’ memory reads, as discussed in Section 5, System Interface,
subsection titled DRAM Interface, Support for External Cache. Detailed timing
diagrams are included in System Timing Relationships.
The 80386sx, unlike the 80286, has the ability to keep the address valid until the Next
Address signal(NA-) is asserted. During AT bus accesses, the 82C836 takes advantage
of this feature to eliminate the need for external address latches between CPU address
and AT bus address. Less expensive transparent buffers (74F245 or equivalent) may be
used instead of latching buffers.
Address bits A20 and A0 receive special treatment in AT-compatible architectures such
as SCATsx, for the following reasons:
• For compatibility with the 8088 and 8086 at address FFFF:10H and above; it is
necessary to force A20 low during CPU accesses to memory in an 80386sx or 80286
based system. The original AT-compatible approach used the GATE A20 signal from
the keyboard controller to accomplish this, but there is considerable time delay in this
approach. With the advent of the PS/2 architectures, a ‘‘Fast Gate A20 ’’ function was
implemented in port92H. SCATsx supports both approaches. Setting 8042 GATE
A20 high or Fast Gate A20 to one allows the modified A20 to track CPU A20 during
CPU accesses. During DMA and Master cycles, the modified A20 always tracks CPU
A20, even if modified A20 is being forced low during CPU accesses.
• During conversion of 16-bit CPU accesses to paired 8-bit AT bus cycles, A0 must be
forced high during the second 8-bit cycle even though CPU A0 is still low.
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