PIC24EP256GU810-I Datasheet, PDF (598/622 Pages) Electronic Film Capacitors, Inc. – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced Analog

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
TABLE A-1: MAJOR SECTION UPDATES (CONTINUED)
Section Name
Update Description
Section 4.0 “Memory
Organization”
Added the Write Latch and Auxiliary Interrupt Vector to the Program Memory
Map (see Figure 4-1).
Updated the All Resets value for the DSRPAG and DSWPAG registers in the
CPU Core Register Maps (see Table 4-1 and Table 4-2).
Updated the All Resets value for the INTCON2 register in the Interrupt
Controller Register Maps (see Table 4-3 through Table 4-6).
Updated the All Resets values for all registers in the Output Compare 1 -
Output Compare 16 Register Map, with the exception of the OCxTMR and
OCxCON1 registers (see Table 4-9).
Removed the DTM bit (TRGCON1<7> from all PWM Generator # Register
Maps (see Table 4-11 through Table 4-17).
Updated the All Resets value for the QEI1IOC register in the QEI1 Register
Map (see Table 4-18).
Updated the All Resets value for the QEI2IOC register in the QEI1 Register
Map (see Table 4-19).
Added Note 4 to the USB OTG Register Map (see Table 4-25)
Updated all addresses in the Real-Time Clock and Calendar Register Map (see
Table 4-34).
Removed RPINR22 from Table 4-37 through Table 4-40.
Updated the All Resets values for all registers in the Peripheral Pin Select Input
Register Maps and modified the RPIN37-RPINR43 registers (see Table 4-37
through Table 4-40).
Added the VREGSF bit (RCON<11>) to the System Control Register Map (see
Table 4-43).
Added the REFOMD bit (PMD4<3>) to the PMD Register Maps (see Table 4-44
through Table 4-47).
Changed the bit range for CNT from <15:0> to <13:0> for all DMAxCNT
registers in the DMAC Register Map (see Table 4-49).
Updated the All Resets value and removed the ANSC15 and ANSC12 bits in
the ANSLEC registers in the PORTC Register Maps (see Table 4-52 and
Table 4-53).
Updated DSxPAG and Page Description of O, Read and U, Read in Table 4-66.
Added Note to the Table 4-67.
Updated Arbiter Architecture in Figure 4-8.
Updated the Unimplemented value and removed the LATG3 and LATG2 bits in
the LATG registers and the CNPUG3 and CNPUG2 bits from the CNPUG
registers in the PORTG Register Maps (see Table 4-60 and Table 4-61)
Section 5.0 “Flash Program
Memory”
Section 6.0 “Resets”
Updated the All Resets value and removed the TRISG3 and TRISG2 bits in the
TRISG registers and the ODCG3 and ODCG2 bits from the ODCG registers in
the PORTG Register Maps (see Table 4-60 and Table 4-61).
Updated the NVMOP<3:0> = 1110 definition to Reserved and added Note 6 to
the Nonvolatile Memory (NVM) Control Register (see Register 5-1).
Added the VREGSF bit (RCON<11>) to the Reset Control Register (see
Register 6-1).
DS70616G-page 598
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