PIC24EP256GU810-I Datasheet, PDF (159/622 Pages) Electronic Film Capacitors, Inc. – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced Analog

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
8.0 DIRECT MEMORY ACCESS
(DMA)
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXX(GP/MC/MU)806/
810/814 and PIC24EPXXX(GP/GU)810/
814 families of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 22. “Direct
Memory Access (DMA)” (DS70348)
of the “dsPIC33E/PIC24E Family
Reference Manual”, which is available
from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The DMA controller transfers data between
peripheral data registers and data space SRAM.
The dsPIC33EPXXX(GP/MC/MU)806/810/814 and
PIC24EPXXX(GP/GU)810/814 DMA subsystem uses
dual-ported SRAM memory (DPSRAM) and register
structures that allow the DMA to operate across its
own, independent address and data buses with no
impact on CPU operation. This architecture eliminates
the need for cycle stealing, which halts the CPU when
a higher priority DMA transfer is requested. Both the
CPU and DMA controller can write and read to/from
FIGURE 8-1:
DMA CONTROLLER
addresses within data space without interference, such
as CPU stalls, resulting in maximized, real-time
performance. Alternatively, DMA operation and data
transfer to/from the memory and peripherals are not
impacted by CPU processing. For example, when a
Run-Time Self-Programming (RTSP) operation is
performed, the CPU does not execute any instructions
until RTSP is finished. This condition, however, does
not impact data transfer to/from memory and the
peripherals.
In addition, DMA can access entire data memory space
(SRAM and DPSRAM). The Data Memory Bus Arbiter
is utilized when either the CPU or DMA attempts to
access non-dual ported SRAM, resulting in potential
DMA or CPU stalls.
The DMA controller supports up to 15 independent
channels. Each channel can be configured for transfers
to or from selected peripherals. Some of the
peripherals supported by the DMA controller include:
• ECAN™
• Data Converter Interface (DCI)
• Analog-to-Digital Converter (ADC)
• Serial Peripheral Interface (SPI)
• UART
• Input Capture
• Output Compare
• Parallel Master Port (PMP)
Refer to Table 8-1 for a complete list of supported
peripherals.
DPSRAM
PERIPHERAL
DMA
Arbiter
 2009-2012 Microchip Technology Inc.
SRAM
DS70616G-page 159