PIC24EP256GU810-I Datasheet, PDF (138/622 Pages) Electronic Film Capacitors, Inc. – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced Analog

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
REGISTER 5-1: NVMCON: NON-VOLATILE MEMORY (NVM) CONTROL REGISTER
R/SO-0⁽¹⁾
R/W-0⁽¹⁾
R/W-0⁽¹⁾
R/W-0
U-0
U-0
U-0
WR
WREN
WRERR NVMSIDL⁽²⁾
—
—
—
bit 15
U-0
—
bit 7
U-0
U-0
U-0
R/W-0⁽¹⁾
R/W-0⁽¹⁾
R/W-0⁽¹⁾
—
—
—
NVMOP<3:0>^(3,4)
U-0
—
bit 8
R/W-0⁽¹⁾
bit 0
Legend:
R = Readable bit
-n = Value at POR
SO = Settable Only bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11-4
bit 3-0
WR: Write Control bit⁽¹⁾
1 = Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is
cleared by hardware once operation is complete
0 = Program or erase operation is complete and inactive
WREN: Write Enable bit⁽¹⁾
1 = Enables Flash program/erase operations
0 = Inhibits Flash program/erase operations
WRERR: Write Sequence Error Flag bit⁽¹⁾
1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically
on any set attempt of the WR bit)
0 = The program or erase operation completed normally
NVMSIDL: NVM Stop-in-Idle Control bit⁽²⁾
1 = Flash voltage regulator goes into Stand-by mode during Idle mode
0 = Flash voltage regulator is active during Idle mode
Unimplemented: Read as ‘0’
NVMOP<3:0>: NVM Operation Select bits^(1,3,4)
1111 = Reserved
1110 = Reserved
1101 = Bulk erase primary program Flash memory
1100 = Reserved
1011 = Reserved
1010 = Bulk erase auxiliary program Flash memory
0011 = Memory page erase operation
0010 = Memory row program operation
0001 = Memory word program operation⁽⁵⁾
0000 = Program a single Configuration register byte
Note 1:
2:
3:
4:
5:
These bits can only be reset on a POR.
If this bit is set, upon exiting Idle mode, there is a delay (TVREG) before Flash memory becomes
operational.
All other combinations of NVMOP<3:0> are unimplemented.
Execution of the PWRSAV instruction is ignored while any of the NVM operations are in progress.
Two adjacent words are programmed during execution of this operation.
DS70616G-page 138
 2009-2012 Microchip Technology Inc.