PIC24EP256GU810-I Datasheet, PDF (328/622 Pages) Electronic Film Capacitors, Inc. – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced Analog

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
REGISTER 17-3: QEIxSTAT: QEIx STATUS REGISTER
U-0
U-0
HS, R/C-0
R/W-0
HS, R/C-0
—
—
PCHEQIRQ PCHEQIEN PCLEQIRQ
bit 15
R/W-0
PCLEQIEN
HS, R/C-0 R/W-0
POSOVIRQ POSOVIEN
bit 8
HS, R/C-0
PCIIRQ⁽¹⁾
bit 7
R/W-0
PCIIEN
HS, R/C-0
VELOVIRQ
R/W-0
VELOVIEN
HS, R/C-0
HOMIRQ
R/W-0
HOMIEN
HS, R/C-0
IDXIRQ
R/W-0
IDXIEN
bit 0
Legend:
R = Readable bit
-n = Value at POR
HS = Hardware Settable bit
W = Writable bit
‘1’ = Bit is set
C = Clearable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
Unimplemented: Read as ‘0’
PCHEQIRQ: Position Counter Greater Than or Equal Compare Status bit
1 = POSxCNT ≥ QEIxGEC
0 = POSxCNT < QEIxGEC
PCHEQIEN: Position Counter Greater Than or Equal Compare Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
PCLEQIRQ: Position Counter Less Than or Equal Compare Status bit
1 = POSxCNT ≤ QEIxLEC
0 = POSxCNT > QEIxLEC
PCLEQIEN: Position Counter Less Than or Equal Compare Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
POSOVIRQ: Position Counter Overflow Status bit
1 = Overflow has occurred
0 = No overflow has occurred
POSOVIEN: Position Counter Overflow Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
PCIIRQ: Position Counter (Homing) Initialization Process Complete Status bit⁽¹⁾
1 = POSxCNT was reinitialized
0 = POSxCNT was not reinitialized
PCIIEN: Position Counter (Homing) Initialization Process Complete interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
VELOVIRQ: Velocity Counter Overflow Status bit
1 = Overflow has occurred
0 = No overflow has not occurred
VELOVIEN: Velocity Counter Overflow Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
HOMIRQ: Status Flag for Home Event Status bit
1 = Home event has occurred
0 = No Home event has occurred
Note 1: This status bit is only applicable to PIMOD<2:0> modes ‘011’ and ‘100’.
DS70616G-page 328
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