PIC24EP256GU810-I Datasheet, PDF (305/622 Pages) Electronic Film Capacitors, Inc. – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced Analog

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
REGISTER 16-11: PWMCONx: PWMx CONTROL REGISTER
HSC-0
FLTSTAT⁽¹⁾
bit 15
HSC-0
CLSTAT⁽¹⁾
HSC-0
TRGSTAT
R/W-0
FLTIEN
R/W-0
CLIEN
R/W-0
TRGIEN
R/W-0
ITB⁽²⁾
R/W-0
MDCS⁽²⁾
bit 8
R/W-0
R/W-0
R/W-0
U-0
DTC<1:0>
DTCP⁽³⁾
—
bit 7
R/W-0
MTBS
R/W-0
CAM^(2,4)
R/W-0
XPRES⁽⁵⁾
R/W-0
IUE⁽²⁾
bit 0
Legend:
R = Readable bit
-n = Value at POR
HSC = Set or Cleared in Hardware
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
FLTSTAT: Fault Interrupt Status bit⁽¹⁾
1 = Fault interrupt is pending
0 = No Fault interrupt is pending
This bit is cleared by setting FLTIEN = 0.
CLSTAT: Current-Limit Interrupt Status bit⁽¹⁾
1 = Current-limit interrupt is pending
0 = No current-limit interrupt is pending
This bit is cleared by setting CLIEN = 0.
TRGSTAT: Trigger Interrupt Status bit
1 = Trigger interrupt is pending
0 = No trigger interrupt is pending
This bit is cleared by setting TRGIEN = 0.
FLTIEN: Fault Interrupt Enable bit
1 = Fault interrupt is enabled
0 = Fault interrupt is disabled and FLTSTAT bit is cleared
CLIEN: Current-Limit Interrupt Enable bit
1 = Current-limit interrupt is enabled
0 = Current-limit interrupt is disabled and CLSTAT bit is cleared
TRGIEN: Trigger Interrupt Enable bit
1 = A trigger event generates an interrupt request
0 = Trigger event interrupts are disabled and TRGSTAT bit is cleared
ITB: Independent Time Base Mode bit⁽²⁾
1 = PHASEx/SPHASEx registers provide time base period for this PWM generator
0 = PTPER register provides timing for this PWM generator
MDCS: Master Duty Cycle Register Select bit⁽²⁾
1 = MDC register provides duty cycle information for this PWM generator
0 = PDCx and SDCx registers provide duty cycle information for this PWM generator
Note 1:
2:
3:
4:
5:
Software must clear the interrupt status here and in the corresponding IFS bit in the interrupt controller.
These bits should not be changed after the PWM is enabled (PTEN = 1).
DTC<1:0> = 11 for DTCP to be effective; otherwise, DTCP is ignored.
The Independent Time Base (ITB = 1) mode must be enabled to use Center-Aligned mode. If ITB = 0, the
CAM bit is ignored.
To operate in External Period Reset mode, the ITB bit must be ‘1’ and the CLMOD bit in the FCLCONx
register must be ‘0’.
 2009-2012 Microchip Technology Inc.
DS70616G-page 305