PIC24EP256GU810-I Datasheet, PDF (324/622 Pages) Electronic Film Capacitors, Inc. – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced Analog

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
17.2 QEI Control Registers
REGISTER 17-1: QEIxCON: QEIx CONTROL REGISTER
R/W-0
QEIEN
bit 15
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
QEISIDL
PIMOD<2:0>⁽¹⁾
R/W-0
R/W-0
IMV<1:0>⁽²⁾
bit 8
U-0
—
bit 7
R/W-0
R/W-0
INTDIV<2:0>⁽³⁾
R/W-0
R/W-0
CNTPOL
R/W-0
GATEN
R/W-0
R/W-0
CCM<1:0>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12-10
bit 9-8
bit 7
QEIEN: Quadrature Encoder Interface Module Counter Enable bit
1 = Module counters are enabled
0 = Module counters are disabled, but SFRs can be read or written to
Unimplemented: Read as ‘0’
QEISIDL: QEI Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
PIMOD<2:0>: Position Counter Initialization Mode Select bits⁽¹⁾
111 = Reserved
110 = Modulo Count mode for position counter
101 = Resets the position counter when the position counter equals the QEIxGEC register
100 = Second index event after home event initializes position counter with contents of the QEIxIC
register
011 = First index event after home event initializes position counter with contents of the QEIxIC
register
010 = Next index input event initializes the position counter with contents of the QEIxIC register
001 = Every index input event resets the position counter
000 = Index input event does not affect position counter
IMV<1:0>: Index Match Value bits⁽²⁾
11 = Index match occurs when QEB = 1 and QEA = 1
10 = Index match occurs when QEB = 1 and QEA = 0
01 = Index match occurs when QEB = 0 and QEA = 1
00 = Index input event does not affect position counter
Unimplemented: Read as ‘0’
Note 1:
2:
3:
When CCM = 10 or CCM = 11, all of the QEI counters operate as timers and the PIMOD<2:0> bits are
ignored.
When CCM = 00, and QEA and QEB values match Index Match Value (IMV), the POSCNTH and
POSCNTL registers are reset.
The selected clock rate should be at least twice the expected maximum quadrature count rate.
DS70616G-page 324
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