PIC24EP256GU810-I Datasheet, PDF (271/622 Pages) Electronic Film Capacitors, Inc. – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced Analog

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
12.0 TIMER1
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXX(GP/MC/MU)806/
810/814 and PIC24EPXXX(GP/GU)810/
814 families of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 11. “Timers”
(DS70362) of the “dsPIC33E/PIC24E
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The Timer1 module is a 16-bit timer, which can serve
as the time counter for the real-time clock, or operate
as a free-running interval timer/counter.
The Timer1 module has the following unique features
over other timers:
• Can be operated from the low-power 32 kHz
crystal oscillator available on the device.
• Can be operated in Asynchronous Counter mode
from an external clock source.
• The external clock input (T1CK) can optionally be
synchronized to the internal device clock and clock
synchronization is performed after the prescaler.
The unique features of Timer1 allow it to be used for
Real-Time Clock (RTC) applications. A block diagram
of Timer1 is shown in Figure 12-1.
The Timer1 module can operate in one of the following
modes:
• Timer mode
• Gated Timer mode
• Synchronous Counter mode
• Asynchronous Counter mode
In Timer and Gated Timer modes, the input clock is
derived from the internal instruction cycle clock (FCY).
In Synchronous and Asynchronous Counter modes,
the input clock is derived from the external clock input
at the T1CK pin.
The Timer modes are determined by the following bits:
• Timer Clock Source Control bit (TCS): T1CON<1>
• Timer Synchronization Control bit (TSYNC):
T1CON<2>
• Timer Gate Control bit (TGATE): T1CON<6>
Timer control bit setting for different operating modes
are given in the Table 12-1.
TABLE 12-1: TIMER MODE SETTINGS
Mode
TCS TGATE TSYNC
Timer
0
0
x
Gated Timer
0
1
x
Synchronous Counter
1
x
1
Asynchronous Counter 1
x
0
FIGURE 12-1:
16-BIT TIMER1 MODULE BLOCK DIAGRAM
SOSCO/
T1CK
SOSCI
Gate
Sync
Falling Edge
Detect
FP⁽¹⁾ _Prescaler
10
(/n)
TCKPS<1:0>
00
Prescaler
(/n)
0
x1
Sync
1
TCKPS<1:0>
LPOSCEN⁽²⁾
TGATE
TSYNC
TCS
1
Set T1IF Flag
0
T1CLK
TGATE
TMR1 ^Reset
Latch
Data
CLK
Comparator ^Equal
PR1
Note 1: FP is the peripheral clock.
2: See Section 9.0 “Oscillator Configuration” for information on enabling the Secondary Oscillator (SOSC).
 2009-2012 Microchip Technology Inc.
DS70616G-page 271