PIC24EP256GU810-I Datasheet, PDF (122/622 Pages) Electronic Film Capacitors, Inc. – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced Analog

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
4.4.1 PAGED MEMORY SCHEME
The dsPIC33EPXXX(GP/MC/MU)806/810/814 and
PIC24EPXXX(GP/GU)810/814 architecture extends
the available data space through a paging scheme,
which allows the available data space to be accessed
using MOV instructions in a linear fashion for pre- and
post-modified Effective Addresses (EA). The upper half
of Base Data Space address is used in conjunction with
the Data Space Page registers, the 10-Bit Read Page
register (DSRPAG) or the 9-Bit Write Page register
(DSWPAG), to form an Extended Data Space (EDS)
address or Program Space Visibility (PSV) address.
The Data Space Page registers are located in the SFR
space.
Construction of the EDS address is shown in Figure 4-1.
When DSRPAG<9> = 0 and the base address bit,
EA<15> = 1, DSRPAG<8:0> is concatenated onto
EA<14:0> to form the 24-bit EDS read address.
Similarly, when the base address bit, EA<15> = 1,
DSWPAG<8:0> is concatenated onto EA<14:0> to form
the 24-bit EDS write address.
EXAMPLE 4-1: EXTENDED DATA SPACE (EDS) READ ADDRESS GENERATION
16-Bit DS EA
Byte
Select
EA<15> = 0
(DSRPAG = Don't Care)
Generate
PSV Address
No EDS Access 0
EA<15>
Y _{DSRPAG<9> 1}
= 1?
Select ^N
DSRPAG
0
DSRPAG<8:0>
9 Bits
EA
EA
15 Bits
24-Bit EDS EA
Note: DS read access when DSRPAG = 0x000 will force an address error trap.
Byte
Select
DS70616G-page 122
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