PIC24EP256GU810-I Datasheet, PDF (481/622 Pages) Electronic Film Capacitors, Inc. – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced Analog

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
29.2 On-Chip Voltage Regulator
All of the dsPIC33EPXXX(GP/MC/MU)806/810/814
and PIC24EPXXX(GP/GU)810/814 devices power
their core digital logic at a nominal 1.8V. This can create
a conflict for designs that are required to operate at a
higher typical voltage, such as 3.3V. To simplify system
design, all devices in the dsPIC33EPXXX(GP/MC/
MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
family incorporate an on-chip regulator that allows the
device to run its core logic from VDD.
The regulator provides power to the core from the other
VDD pins. A low-ESR (less than 1 Ohms) capacitor
(such as tantalum or ceramic) must be connected to the
VCAP pin (Figure 29-1). This helps to maintain the
stability of the regulator. The recommended value for
the filter capacitor is provided in Table 32-13 located in
Section 32.0 “Electrical Characteristics”.
Note:
It is important for the low-ESR capacitor to
be placed as close as possible to the VCAP
pin.
FIGURE 29-1:
CONNECTIONS FOR THE
ON-CHIP VOLTAGE
REGULATOR^(1,2,3)
3.3V
dsPIC33E/PIC24E
CEFC
VDD
VCAP
VSS
29.3 Brown-out Reset (BOR)
The Brown-out Reset module is based on an internal
voltage reference circuit that monitors the regulated
supply voltage, VCAP. The main purpose of the BOR
module is to generate a device Reset when a brown-
out condition occurs. Brown-out conditions are
generally caused by glitches on the AC mains (for
example, missing portions of the AC cycle waveform
due to bad power transmission lines, or voltage sags
due to excessive current draw when a large inductive
load is turned on).
A BOR generates a Reset pulse, which resets the
device. The BOR selects the clock source based on the
device Configuration bit values (FNOSC<2:0> and
POSCMD<1:0>).
If an oscillator mode is selected, the BOR activates the
Oscillator Start-up Timer (OST). The system clock is
held until OST expires. If the PLL is used, the clock is
held until the LOCK bit (OSCCON<5>) is ‘1’.
Concurrently, the Power-up Timer (PWRT) Time-out
(TPWRT) is applied before the internal Reset is
released. If TPWRT = 0 and a crystal oscillator is
being used, then a nominal delay of TFSCM is
applied. The total delay in this case is TFSCM. Refer
to Parameter SY35 in Table 32-22 of Section 32.0
“Electrical Characteristics” for specific TFSCM
values.
The BOR Status bit (RCON<1>) is set to indicate that a
BOR has occurred. The BOR circuit, continues to oper-
ate while in Sleep or Idle modes and resets the device
should VDD fall below the BOR threshold voltage.
Note 1:
2:
3:
These are typical operating voltages. Refer
to Table 32-13 located in Section 32.1
“DC Characteristics” for the full operating
ranges of VDD and VCAP.
It is important for the low-ESR capacitor to
be placed as close as possible to the VCAP
pin.
Typical VCAP pin voltage is 1.8V when
VDD  VDDMIN.
 2009-2012 Microchip Technology Inc.
DS70616G-page 481