PIC24EP256GU810-I Datasheet, PDF (297/622 Pages) Electronic Film Capacitors, Inc. – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced Analog

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
16.2 PWM Control Registers
REGISTER 16-1: PTCON: PWM TIME BASE CONTROL REGISTER
R/W-0
PTEN
bit 15
U-0
R/W-0
HSC-0
R/W-0
R/W-0
—
PTSIDL
SESTAT
SEIEN
EIPU⁽¹⁾
R/W-0
R/W-0
SYNCPOL⁽¹⁾ SYNCOEN⁽¹⁾
bit 8
R/W-0
SYNCEN⁽¹⁾
bit 7
R/W-0
R/W-0
R/W-0
SYNCSRC<2:0>⁽¹⁾
R/W-0
R/W-0
R/W-0
SEVTPS<3:0>⁽¹⁾
R/W-0
bit 0
Legend:
R = Readable bit
-n = Value at POR
HSC = Hardware Settable/Clearable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
PTEN: PWM Module Enable bit
1 = PWM module is enabled
0 = PWM module is disabled
Unimplemented: Read as ‘0’
PTSIDL: PWM Time Base Stop in Idle Mode bit
1 = PWM time base halts in CPU Idle mode
0 = PWM time base runs in CPU Idle mode
SESTAT: Special Event Interrupt Status bit
1 = Special event interrupt is pending
0 = Special event interrupt is not pending
SEIEN: Special Event Interrupt Enable bit
1 = Special event interrupt is enabled
0 = Special event interrupt is disabled
EIPU: Enable Immediate Period Updates bit⁽¹⁾
1 = Active Period register is updated immediately
0 = Active Period register updates occur on PWM cycle boundaries
SYNCPOL: Synchronize Input and Output Polarity bit⁽¹⁾
1 = SYNCIx/SYNCO polarity is inverted (active-low)
0 = SYNCIx/SYNCO is active-high
SYNCOEN: Primary Time Base Sync Enable bit⁽¹⁾
1 = SYNCO output is enabled
0 = SYNCO output is disabled
SYNCEN: External Time Base Synchronization Enable bit⁽¹⁾
1 = External synchronization of primary time base is enabled
0 = External synchronization of primary time base is disabled
Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCIx feature, the user
application must program the Period register with a value that is slightly larger than the expected period of
the external synchronization input signal.
 2009-2012 Microchip Technology Inc.
DS70616G-page 297