PIC24EP256GU810-I Datasheet, PDF (145/622 Pages) Electronic Film Capacitors, Inc. – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced Analog

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
7.0 INTERRUPT CONTROLLER
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXX(GP/MC/MU)806/
810/814 and PIC24EPXXX(GP/GU)810/
814 families of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 6. “Inter-
rupts” (DS70600) of the “dsPIC33E/
PIC24E Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The dsPIC33EPXXX(GP/MC/MU)806/810/814 and
PIC24EPXXX(GP/GU)810/814 interrupt controller
reduces the numerous peripheral interrupt request
signals to a single interrupt request signal to
the dsPIC33EPXXX(GP/MC/MU)806/810/814 and
PIC24EPXXX(GP/GU)810/814 CPU.
The interrupt controller has the following features:
• Up to eight processor exceptions and software
traps
• Eight user-selectable priority levels
• Interrupt Vector Table (IVT) with a unique vector
for each interrupt or exception source
• Fixed priority within a specified user priority level
• Fixed interrupt entry and return latencies
7.1 Interrupt Vector Table
The dsPIC33EPXXX(GP/MC/MU)806/810/814 and
PIC24EPXXX(GP/GU)810/814 Interrupt Vector Table
(IVT), shown in Figure 7-1, resides in the General
Segment of program memory, starting at location,
0x000004, and is used when executing code from the
General Segment. The IVT contains seven non-
maskable trap vectors and up to 114 sources of
interrupt. In general, each interrupt source has its own
vector. Each interrupt vector contains a 24-bit wide
address. The value programmed into each interrupt
vector location is the starting address of the associated
Interrupt Service Routine (ISR).
Interrupt vectors are prioritized in terms of their natural
priority. This priority is linked to their position in the
vector table. Lower addresses generally have a higher
natural priority. For example, the interrupt associated
with vector 0 takes priority over interrupts at any other
vector address.
Note:
Any unimplemented or unused vector
locations in the IVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESET instruction.
7.2 Auxiliary Interrupt Vector
When code is being executed in the Auxiliary Segment,
a special single interrupt vector, located at address,
0x7FFFFA, is used for all interrupt sources and traps.
Once vectored to this single routine, the
VECNUM<7:0> bits (INTTREG<7:0>, Register 7-7)
can be examined to determine the source of the
interrupt or trap so that it can be properly processed.
7.3 Reset Sequence
A device Reset is not a true exception because the
interrupt controller is not involved in the Reset process.
The dsPIC33EPXXX(GP/MC/MU)806/810/814 and
PIC24EPXXX(GP/GU)810/814 devices clear their
registers in response to a Reset, which forces the PC
to zero. The digital signal controller then begins
program execution at location, 0x000000. A GOTO
instruction at the Reset address can redirect program
execution to the appropriate start-up routine.
Note:
Reset locations are also located in the
Auxiliary Segment at the addresses
0x7FFFFC and 0x7FFFFE. The Reset
Target Vector Select bit, RSTPRI
(FICD<2>) controls whether the primary
(General Segment) or Auxiliary Segment
Reset location is used.
 2009-2012 Microchip Technology Inc.
DS70616G-page 145