PIC24EP256GU810-I Datasheet, PDF (339/622 Pages) Electronic Film Capacitors, Inc. – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced Analog

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
18.3 SPI Control Registers
REGISTER 18-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER
R/W-0
SPIEN
bit 15
U-0
R/W-0
U-0
—
SPISIDL
—
U-0
R/W-0
—
R/W-0
SPIBEC<2:0>
R/W-0
bit 8
R/W-0
SRMPT
bit 7
R/C-0, HS
SPIROV
R/W-0
SRXMPT
R/W-0
R/W-0
SISEL<2:0>
R/W-0
R-0, HS, HC
SPITBF
R-0, HS, HC
SPIRBF
bit 0
Legend:
R = Readable bit
-n = Value at POR
HS = Hardware Settable bit
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
HC = Hardware Clearable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
bit 15
bit 14
bit 13
bit 12-11
bit 10-8
bit 7
bit 6
bit 5
bit 4-2
SPIEN: SPIx Enable bit
1 = Enables the module and configures SCKx, SDOx, SDIx and SSx as serial port pins
0 = Disables the module
Unimplemented: Read as ‘0’
SPISIDL: SPIx Stop in Idle Mode bit
1 = Discontinues the module operation when device enters Idle mode
0 = Continues the module operation in Idle mode
Unimplemented: Read as ‘0’
SPIBEC<2:0>: SPIx Buffer Element Count bits (valid in Enhanced Buffer mode)
Master mode:
Number of SPIx transfers that are pending.
Slave mode:
Number of SPIx transfers that are unread.
SRMPT: SPIx Shift Register (SPIxSR) Empty bit (valid in Enhanced Buffer mode)
1 = SPIx Shift register is empty and Ready-to-Send or receive the data
0 = SPIx Shift register is not empty
SPIROV: SPIx Receive Overflow Flag bit
1 = A new byte/word is completely received and discarded; the user application has not read the
previous data in the SPIxBUF register
0 = No overflow has occurred
SRXMPT: SPIx Receive FIFO Empty bit (valid in Enhanced Buffer mode)
1 = RX FIFO is empty
0 = RX FIFO is not empty
SISEL<2:0>: SPIx Buffer Interrupt Mode bits (valid in Enhanced Buffer mode)
111 = Interrupt when the SPIx transmit buffer is full
110 = Interrupt when last bit is shifted into SPIxSR, and as a result, the TX FIFO is empty
101 = Interrupt when the last bit is shifted out of SPIxSR and the transmit is complete
100 = Interrupt when one data is shifted into the SPIxSR, and as a result, the TX FIFO has one open
memory location
011 = Interrupt when the SPIx receive buffer is full
010 = Interrupt when the SPIx receive buffer is 3/4 or more full
001 = Interrupt when data is available in the receive buffer (SRMPT bit is set)
000 = Interrupt when the last data in the receive buffer is read, and as a result, the buffer is empty
(SRXMPT bit is set)
 2009-2012 Microchip Technology Inc.
DS70616G-page 339