PIC24EP256GU810-I Datasheet, PDF (479/622 Pages) Electronic Film Capacitors, Inc. – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced Analog

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
TABLE 29-2: CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field Register RTSP Effect
Description
WINDIS
FWDT Immediate ^{Watchdog Timer Window Enable bit}
1 = Watchdog Timer is in Non-Window mode
0 = Watchdog Timer is in Window mode
PLLKEN
FWDT Immediate PLL Lock Wait Enable bit
1 = Clock switches to the PLL source will wait until the PLL lock signal is valid
0 = Clock switch will not wait for PLL lock
WDTPRE
FWDT Immediate Watchdog Timer Prescaler bit
APLK<1:0>
FAS⁽²⁾
Immediate
1 = 1:128
0 = 1:32
Auxiliary Segment Key bits
These bits must be set to ‘00’ if AWRP = 1 and APL = 1. These bits must
be set to ‘11’ for any other value of the AWRP and APL bits.
Any mismatch between either the AWRP or APL bits and the APLK bits
(as described above), will result in code protection becoming enabled for
the Auxiliary Segment. A Flash bulk erase will be required to unlock the
device.
APL
FAS⁽²⁾ Immediate Auxiliary Segment Code-Protect bit
AWRP
FAS⁽²⁾
Immediate
1 = Auxiliary program memory is not code-protected
0 = Auxiliary program memory is code-protected
Auxiliary Segment Write-Protect bit
1 = Auxiliary program memory is not write-protected
0 = Auxiliary program memory is write-protected
WDTPOST<3:0> FWDT Immediate Watchdog Timer Postscaler bits
1111 = 1:32,768
1110 = 1:16,384
•
•
•
0001 = 1:2
0000 = 1:1
FPWRT<2:0>
FPOR Immediate Power-on Reset Timer Value Select bits
BOREN⁽¹⁾
FPOR
Immediate
111 = PWRT = 128 ms
110 = PWRT = 64 ms
101 = PWRT = 32 ms
100 = PWRT = 16 ms
011 = PWRT = 8 ms
010 = PWRT = 4 ms
001 = PWRT = 2 ms
000 = PWRT = Disabled
Brown-out Reset (BOR) Detection Enable bit
ALTI2C2
FPOR
Immediate
1 = BOR is enabled
0 = BOR is disabled
Alternate I²C™ pins for I2C2 bit
ALTI2C1
FPOR
Immediate
1 = I2C2 is mapped to the SDA2/SCL2 pins
0 = I2C2 is mapped to the ASDA2/ASCL2 pins
Alternate I²C pins for I2C1 bit
1 = I2C1 is mapped to the SDA1/SCL1 pins
0 = I2C1 is mapped to the ASDA1/ASCL1 pins
Note 1: BOR should always be enabled for proper operation (BOREN = 1).
2: This register can only be modified when code protection and write protection are disabled for both the
General and Auxiliary Segments (APL = 1, AWRP = 1, APLK = 0, GSS = 1, GWRP = 1 and GSSK = 0).
 2009-2012 Microchip Technology Inc.
DS70616G-page 479