PIC24EP256GU810-I Datasheet, PDF (513/622 Pages) Electronic Film Capacitors, Inc. – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced Analog

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
TABLE 32-17: PLL CLOCK TIMING SPECIFICATIONS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
Param. Symbol
Characteristic
Min. Typ.⁽¹⁾ Max. Units
Conditions
OS50 FPLLI
PLL Voltage Controlled
Oscillator (VCO) Input
Frequency Range
0.8
—
8.0 MHz ECPLL, XTPLL modes
OS51 FSYS
On-Chip VCO System
Frequency
120
—
340 MHz
OS52 TLOCK PLL Start-up Time (Lock Time) 0.9
1.5
3.1
mS
OS53 DCLK
CLKO Stability (Jitter)⁽²⁾
-5
0.5
5
%
Note 1:
2:
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
This jitter specification is based on clock cycle-by-clock cycle measurements. To get the effective jitter for
individual time bases or communication clocks used by the application, use the following formula:
Effective Jitter = ---------------------------------------^D-----^C---^L---^K-----------------------------------------
T^----i^--m^----e^----B^----a^---s^--e^----o^---r^----C^---F-o^---m^O----Sm^---C--u^---n^---i^-c^---a^---t^--i^-o^---n^-----C^----l^--o^---c^--k^-
For example, if FOSC = 120 MHz and the SPI bit rate = 10 MHz, the effective jitter is as follows:
Effective Jitter
=
D_-----C_----L_---K_-
1--1-2--0-0--
=
D_-----C_----L_---K_-
12
=
-^D_3---.-^C-4---6^L---4^K-
TABLE 32-18: AUXILIARY PLL CLOCK TIMING SPECIFICATIONS
(dsPIC33EPXXXMU8XX AND PIC24EPXXXGU8XX DEVICES ONLY)
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise
stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
Param. Symbol
Characteristic
Min. Typ.⁽¹⁾ Max. Units
Conditions
OS54
AFPLLI
PLL Voltage Controlled
Oscillator (VCO) Input
Frequency Range
3
—
5.5 MHz ECPLL, XTPLL modes
OS55 AFSYS On-Chip VCO System
Frequency
60
—
120 MHz
OS56 ATLOCK PLL Start-up Time (Lock Time) 0.9
1.5
3.1
mS
OS57 ADCLK CLKO Stability (Jitter)
-2
0.25
2
%
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
 2009-2012 Microchip Technology Inc.
DS70616G-page 513