PIC24EP256GU810-I Datasheet, PDF (125/622 Pages) Electronic Film Capacitors, Inc. – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced Analog

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
Allocating different Page registers for read and write
access allows the architecture to support data
movement between different pages in data memory.
This is accomplished by setting the DSRPAG register
value to the page from which you want to read and
configuring the DSWPAG register to the page to which
it needs to be written. Data can also be moved from
different PSV to EDS pages, by configuring the
DSRPAG and DSWPAG registers to address PSV and
EDS space, respectively. The data can be moved
between pages by a single instruction.
When an EDS or PSV page overflow or underflow
occurs, EA<15> is cleared as a result of the register
indirect EA calculation. An overflow or underflow of the
EA in the EDS or PSV pages can occur at the page
boundaries when:
• The initial address, prior to modification,
addresses an EDS or PSV page.
• The EA calculation uses Pre- or Post-Modified
Register Indirect Addressing. However, this does
not include Register Offset Addressing.
In general, when an overflow is detected, the DSxPAG
register is incremented and the EA<15> bit is set to
keep the base address within the EDS or PSV window.
When an underflow is detected, the DSxPAG register is
decremented and the EA<15> bit is set to keep the
base address within the EDS or PSV window. This
creates a linear EDS and PSV address space, but only
when using Register Indirect Addressing modes.
Exceptions to the operation described above arise
when entering and exiting the boundaries of Page 0,
EDS and PSV spaces. Table 4-73 lists the effects of
overflow and underflow scenarios at different
boundaries.
In the following cases, when overflow or underflow
occurs, the EA<15> bit is set and the DSxPAG is not
modified; therefore, the EA will wrap to the beginning of
the current page:
• Register Indirect with Register Offset Addressing
• Modulo Addressing
• Bit-Reversed Addressing
TABLE 4-73: OVERFLOW AND UNDERFLOW SCENARIOS AT PAGE 0, EDS and
PSV SPACE BOUNDARIES^(2,3,4)
O/U,
R/W
Operation
DSxPAG
Before
DS
EA<15>
Page
Description
DSxPAG
After
DS
EA<15>
Page
Description
O,
Read
DSRPAG = 0x1FF
1 EDS: Last page DSRPAG = 0x1FF
0 See Note 1
O,
Read
O,
Read
[++Wn]
or
[Wn++]
DSRPAG = 0x2FF
DSRPAG = 0x3FF
1 PSV: Last lsw DSRPAG = 0x300
page
1 PSV: Last MSB DSRPAG = 0x3FF
page
1 PSV: First MSB
page
0 See Note 1
O,
Write
DSWPAG = 0x1FF
1 EDS: Last page DSWPAG = 0x1FF
0 See Note 1
U,
Read
U,
Read
U,
Read
DSRPAG = 0x001
[--Wn]
or
[Wn--]
DSRPAG = 0x200
DSRPAG = 0x300
1 EDS page
DSRPAG = 0x001
1 PSV: First lsw DSRPAG = 0x200
page
1 PSV: First MSB DSRPAG = 0x2FF
page
0 See Note 1
0 See Note 1
1 PSV: Last lsw
page
Legend: O = Overflow, U = Underflow, R = Read, W = Write
Note 1: Register Indirect Addressing now addresses a location in the Base Data Space (0x0000-0x8000).
2: An EDS access with DSxPAG = 0x000 will generate an address error trap.
3: Only reads from PS are supported using DSRPAG. An attempt to write to PS using DSWPAG will generate
an address error trap.
4: Pseudo-Linear Addressing is not supported for large offsets.
 2009-2012 Microchip Technology Inc.
DS70616G-page 125