PIC24EP256GU810-I Datasheet, PDF (164/622 Pages) Electronic Film Capacitors, Inc. – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced Analog

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
REGISTER 8-2: DMAXREQ: DMA CHANNEL X IRQ SELECT REGISTER
R/S-0
U-0
U-0
U-0
U-0
U-0
U-0
FORCE⁽¹⁾
—
—
—
—
—
—
bit 15
U-0
—
bit 8
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
IRQSEL<7:0>
R/W-0
R/W-0
R/W-0
bit 0
Legend:
R = Readable bit
-n = Value at POR
S = Settable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14-8
bit 7-0
FORCE: Force DMA Transfer bit⁽¹⁾
1 = Forces a single DMA transfer (Manual mode)
0 = Automatic DMA transfer initiation by DMA request
Unimplemented: Read as ‘0’
IRQSEL<7:0>: DMA Peripheral IRQ Number Select bits
00000000 = INT0 – External Interrupt 0
00000001 = IC1 – Input Capture 1
00000010 = OC1 – Output Compare 1
00000101 = IC2 – Input Capture 2
00000110 = OC2 – Output Compare 2
00000111 = TMR2 – Timer2
00001000 = TMR3 – Timer3
00001010 = SPI1 – Transfer done
00001011 = UART1RX – UART1 Receiver
00001100 = UART1TX – UART1 Transmitter
00001101 = ADC1 – ADC1 convert done
00010101 = ADC2 – ADC2 convert done
00011001 = OC3 – Output Compare 3
00011010 = OC4 – Output Compare 4
00011011 = TMR4 – Timer4
00011100 = TMR5 – Timer5
00011110 = UART2RX – UART2 Receiver
00011111 = UART2TX – UART2 Transmitter
00100001 = SPI2 – Transfer done
00100010 = ECAN1 – RX data ready
00100101 = IC3 – Input Capture 3
00100110 = IC4 – Input Capture 4
00101101 = PMP Data mode
00110111 = ECAN2 – RX data ready
00111100 = DCI – DCI transfer done
01000110 = ECAN1 – TX data request
01000111 = ECAN2 – TX data request
01010010 = UART3RX – UART3 Receiver
01010011 = UART3TX – UART3 Transmitter
01011000 = UART4RX – UART4 Receiver
01011001 = UART4TX – UART4 Transmitter
01011011 = SPI3 – Transfer done
01111011 = SPI4 – Transfer done
Note 1: The FORCE bit cannot be cleared by user software. The FORCE bit is cleared by hardware when the
forced DMA transfer is complete or the channel is disabled (CHEN = 0).
DS70616G-page 164
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