PIC24EP256GU810-I Datasheet, PDF (153/622 Pages) Electronic Film Capacitors, Inc. – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced Analog

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1
R/W-0
NSTDIS
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
OVAERR⁽¹⁾ OVBERR⁽¹⁾ COVAERR⁽¹⁾ COVBERR⁽¹⁾
R/W-0
OVATE⁽¹⁾
R/W-0
OVBTE⁽¹⁾
R/W-0
COVTE⁽¹⁾
bit 8
R/W-0
SFTACERR⁽¹⁾
bit 7
R/W-0
DIV0ERR
R/W-0
DMACERR
R/W-0
MATHERR
R/W-0
ADDRERR
R/W-0
STKERR
R/W-0
OSCFAIL
U-0
—
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
NSTDIS: Interrupt Nesting Disable bit
1 = Interrupt nesting is disabled
0 = Interrupt nesting is enabled
OVAERR: Accumulator A Overflow Trap Flag bit⁽¹⁾
1 = Trap was caused by overflow of Accumulator A
0 = Trap was not caused by overflow of Accumulator A
OVBERR: Accumulator B Overflow Trap Flag bit⁽¹⁾
1 = Trap was caused by overflow of Accumulator B
0 = Trap was not caused by overflow of Accumulator B
COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit⁽¹⁾
1 = Trap was caused by catastrophic overflow of Accumulator A
0 = Trap was not caused by catastrophic overflow of Accumulator A
COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit⁽¹⁾
1 = Trap was caused by catastrophic overflow of Accumulator B
0 = Trap was not caused by catastrophic overflow of Accumulator B
OVATE: Accumulator A Overflow Trap Enable bit⁽¹⁾
1 = Trap overflow of Accumulator A
0 = Trap is disabled
OVBTE: Accumulator B Overflow Trap Enable bit⁽¹⁾
1 = Trap overflow of Accumulator B
0 = Trap is disabled
COVTE: Catastrophic Overflow Trap Enable bit⁽¹⁾
1 = Trap on catastrophic overflow of Accumulator A or B is enabled
0 = Trap is disabled
SFTACERR: Shift Accumulator Error Status bit⁽¹⁾
1 = Math error trap was caused by an invalid accumulator shift
0 = Math error trap was not caused by an invalid accumulator shift
DIV0ERR: Divide-by-Zero Error Status bit
1 = Math error trap was caused by a divide-by-zero
0 = Math error trap was not caused by a divide-by-zero
DMACERR: DMAC Trap Flag bit
1 = DMAC trap has occurred
0 = DMAC trap has not occurred
Note 1: This bit is available on dsPIC33EPXXX(GP/MC/MU)806/810/814 devices only.
 2009-2012 Microchip Technology Inc.
DS70616G-page 153