PIC24EP256GU810-I Datasheet, PDF (281/622 Pages) Electronic Film Capacitors, Inc. – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced Analog

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
14.0 INPUT CAPTURE
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXX(GP/MC/MU)806/
810/814 and PIC24EPXXX(GP/GU)810/
814 families of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 12. “Input
Capture” (DS70352) of the “dsPIC33E/
PIC24E Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The input capture module is useful in applications
requiring frequency (period) and pulse measurement.
The dsPIC33EPXXX(GP/MC/MU)806/810/814 and
PIC24EPXXX(GP/GU)810/814 devices support up to
16 input capture channels.
Key features of the input capture module include:
• Hardware-configurable for 32-bit operation in all
modes by cascading two adjacent modules
• Synchronous and Trigger modes of output
compare operation, with up to 30 user-selectable
Trigger/Sync sources available
• A 4-level FIFO buffer for capturing and holding
timer values for several events
• Configurable interrupt generation
• Up to six clock sources available for each module,
driving a separate internal 16-bit counter
Note:
Only IC1, IC2, IC3 and IC4 can trigger a
DMA data transfer. If DMA data transfers
are required, the FIFO buffer size must be
set to ‘1’ (ICI<1:0> = 00).
FIGURE 14-1:
INPUT CAPTURE MODULE BLOCK DIAGRAM
ICM<2:0>
ICI<1:0>
ICx Pin
Prescaler
Counter
1:1/4/16
ICTSEL<2:0>
Edge Detect Logic
and
Clock Synchronizer
Event and
Interrupt
Logic
Set ICxIF
FP
T1CLK
Clock
Select
Increment
ICxTMR
16
4-Level FIFO Buffer
16
T5CLK
Trigger and
Sync Sources
Trigger and
Sync Logic
Reset
SYNCSEL<4:0>
Trigger⁽¹⁾
ICxBUF
ICOV, ICBNE
16
System Bus
Note 1: The Trigger/Sync source is enabled by default and is set to Timer3 as a source. This timer must be enabled for
proper ICx module operation or the Trigger/Sync source must be changed to another source option.
 2009-2012 Microchip Technology Inc.
DS70616G-page 281