PIC24EP256GU810-I Datasheet, PDF (348/622 Pages) Electronic Film Capacitors, Inc. – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced Analog

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
19.2 I²C Control Registers
REGISTER 19-1: I2CxCON: I2Cx CONTROL REGISTER
R/W-0
U-0
I2CEN
—
bit 15
R/W-0
I2CSIDL
R/W-1, HC
SCLREL
R/W-0
IPMIEN⁽¹⁾
R/W-0
A10M
R/W-0
DISSLW
R/W-0
SMEN
bit 8
R/W-0
GCEN
bit 7
R/W-0
STREN
R/W-0
ACKDT
R/W-0, HC R/W-0, HC
ACKEN
RCEN
R/W-0, HC
PEN
R/W-0, HC
RSEN
R/W-0, HC
SEN
bit 0
Legend:
R = Readable bit
-n = Value at POR
HC = Hardware Clearable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
I2CEN: I2Cx Enable bit
1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins
0 = Disables the I2Cx module; all I²C™ pins are controlled by port functions
Unimplemented: Read as ‘0’
I2CSIDL: I2Cx Stop in Idle Mode bit
1 = Discontinues module operation when device enters an Idle mode
0 = Continues module operation in Idle mode
SCLREL: SCLx Release Control bit (when operating as I²C slave)
1 = Releases SCLx clock
0 = Holds SCLx clock low (clock stretch)
If STREN = 1:
The bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware is clear
at beginning of every slave data byte transmission. Hardware is clear at the end of every slave address
byte reception. Hardware is clear at end of every slave data byte reception.
If STREN = 0:
The bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware is clear at beginning of every
slave data byte transmission. Hardware is clear at the end of every slave address byte reception.
IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit⁽¹⁾
1 = IPMI mode is enabled; all addresses Acknowledged
0 = IPMI mode is disabled
A10M: 10-Bit Slave Address bit
1 = I2CxADD is a 10-bit slave address
0 = I2CxADD is a 7-bit slave address
DISSLW: Disable Slew Rate Control bit
1 = Slew rate control is disabled
0 = Slew rate control is enabled
SMEN: SMBus Input Levels bit
1 = Enables I/O pin thresholds compliant with the SMBus specification
0 = Disables SMBus input thresholds
GCEN: General Call Enable bit (when operating as I²C slave)
1 = Enables interrupt when a general call address is received in the I2CxRSR (module is enabled for reception)
0 = General call address is disabled
Note 1: When performing master operations, ensure that the IPMIEN bit is ‘0’.
DS70616G-page 348
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