PIC24EP256GU810-I Datasheet, PDF (42/622 Pages) Electronic Film Capacitors, Inc. – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced Analog

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
3.7 CPU Control Registers
REGISTER 3-1: SR: CPU STATUS REGISTER
R/W-0
OA⁽¹⁾
bit 15
R/W-0
OB⁽¹⁾
R/W-0
SA^(1,4)
R/W-0
SB^(1,4)
R/W-0^(2,3)
R/W-0^(2,3) R/W-0^(2,3)
R-0
IPL<2:0>
RA
bit 7
R/C-0
OAB⁽¹⁾
R/W-0
N
R/C-0
SAB⁽¹⁾
R/W-0
OV
R -0
DA⁽¹⁾
R/W-0
Z
R/W-0
DC
bit 8
R/W-0
C
bit 0
Legend:
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
W = Writable bit
C = Clearable bit
‘1’= Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
OA: Accumulator A Overflow Status bit⁽¹⁾
1 = Accumulator A has overflowed
0 = Accumulator A has not overflowed
OB: Accumulator B Overflow Status bit⁽¹⁾
1 = Accumulator B has overflowed
0 = Accumulator B has not overflowed
SA: Accumulator A Saturation ‘Sticky’ Status bit^(1,4)
1 = Accumulator A is saturated or has been saturated at some time
0 = Accumulator A is not saturated
SB: Accumulator B Saturation ‘Sticky’ Status bit^(1,4)
1 = Accumulator B is saturated or has been saturated at some time
0 = Accumulator B is not saturated
OAB: OA || OB Combined Accumulator Overflow Status bit⁽¹⁾
1 = Accumulators A or B have overflowed
0 = Neither Accumulators A or B have overflowed
SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit⁽¹⁾
1 = Accumulators A or B are saturated or have been saturated at some time
0 = Neither Accumulator A or B are saturated
DA: DO Loop Active bit⁽¹⁾
1 = DO loop in progress
0 = DO loop not in progress
DC: MCU ALU Half Carry/Borrow bit
1 = A carry-out from the 4th low order bit (for byte-sized data) or 8th low order bit (for word-sized data)
of the result occurred
0 = No carry-out from the 4th low order bit (for byte-sized data) or 8th low order bit (for word-sized
data) of the result occurred
Note 1:
2:
3:
4:
This bit is available on dsPIC33EPXXX(GP/MC/MU)806/810/814 devices only.
The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL, if IPL<3> = 1.
The IPL<2:0> bits are read-only when NSTDIS = 1 (INTCON1<15>).
A data write to the SR register can modify the SA and SB bits by either a data write to SA and SB or by
clearing the SAB bit. To avoid a possible SA or SB bit write race condition, the SA and SB bits should not
be modified using bit operations.
DS70616G-page 42
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