PIC24EP256GU810-I Datasheet, PDF (478/622 Pages) Electronic Film Capacitors, Inc. – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced Analog

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
TABLE 29-2: CONFIGURATION BITS DESCRIPTION
Bit Field Register RTSP Effect
Description
GSSK<1:0>
FGS
Immediate
General Segment Key bits
These bits must be set to ‘00’ if GWRP = 1 and GSS = 1. These bits must
be set to ‘11’ for any other value of the GWRP and GSS bits.
Any mismatch between either the GWRP or GSS bits, and the GSSK bits
(as described above), will result in code protection becoming enabled for
the General Segment. A Flash bulk erase will be required to unlock the
device.
GSS
FGS
Immediate General Segment Code-Protect bit
1 = User program memory is not code-protected
0 = User program memory is code-protected
GWRP
FGS
Immediate General Segment Write-Protect bit
1 = User program memory is not write-protected
0 = User program memory is write-protected
IESO
FOSCSEL Immediate Two-Speed Oscillator Start-up Enable bit
1 = Start-up device with FRC, then automatically switch to the
user-selected oscillator source when ready
0 = Start-up device with user-selected oscillator source
FNOSC<2:0>
FOSCSEL If clock switch Initial Oscillator Source Selection bits
is enabled, the _{111 = Internal Fast RC (FRC) Oscillator with Postscaler}
RTSP effect is _{110 = Internal Fast RC (FRC) Oscillator with Divide-by-16}
on any device _{101 = LPRC Oscillator}
Reset; _{100 = Secondary (LP) Oscillator}
otherwise, _{011 = Primary (XT, HS, EC) Oscillator with PLL}
immediate _{010 = Primary (XT, HS, EC) Oscillator}
001 = Internal Fast RC (FRC) Oscillator with PLL
000 = FRC Oscillator
FCKSM<1:0>
FOSC Immediate Clock Switching Mode bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
IOL1WAY
FOSC Immediate Peripheral Pin Select Configuration bit
1 = Allows only one reconfiguration
0 = Allows multiple reconfigurations
OSCIOFNC
FOSC Immediate OSC2 Pin Function bit (except in XT and HS modes)
1 = OSC2 is the clock output
0 = OSC2 is the general purpose digital I/O pin
POSCMD<1:0> FOSC Immediate Primary Oscillator Mode Select bits
11 = Primary Oscillator is disabled
10 = HS Crystal Oscillator mode
01 = XT Crystal Oscillator mode
00 = EC (External Clock) mode
FWDTEN
FWDT Immediate Watchdog Timer Enable bit
1 = Watchdog Timer is always enabled (LPRC Oscillator cannot be disabled.
Clearing the SWDTEN bit in the RCON register has no effect.)
0 = Watchdog Timer is enabled/disabled by user software (LPRC can be
disabled by clearing the SWDTEN bit in the RCON register.)
Note 1: BOR should always be enabled for proper operation (BOREN = 1).
2: This register can only be modified when code protection and write protection are disabled for both the
General and Auxiliary Segments (APL = 1, AWRP = 1, APLK = 0, GSS = 1, GWRP = 1 and GSSK = 0).
DS70616G-page 478
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