PIC24EP256GU810-I Datasheet, PDF (44/622 Pages) Electronic Film Capacitors, Inc. – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced Analog

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
REGISTER 3-2:
R/W-0
VAR
bit 15
CORCON: CORE CONTROL REGISTER
U-0
R/W-0
R/W-0
R/W-0
—
US<1:0>⁽¹⁾
EDT^(1,2)
R-0
R-0
DL<2:0>⁽¹⁾
R-0
bit 8
R/W-0
SATA⁽¹⁾
bit 7
R/W-0
SATB⁽¹⁾
R/W-1
R/W-0
SATDW⁽¹⁾ ACCSAT⁽¹⁾
R/C-0
IPL3⁽³⁾
R-0
SFA
R/W-0
RND⁽¹⁾
R/W-0
IF⁽¹⁾
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13-12
bit 11
bit 10-8
bit 7
bit 6
bit 5
bit 4
bit 3
VAR: Variable Exception Processing Latency Control bit
1 = Variable exception processing is enabled
0 = Fixed exception processing is enabled
Unimplemented: Read as ‘0’
US<1:0>: DSP Multiply Unsigned/Signed Control bits⁽¹⁾
11 = Reserved
10 = DSP engine multiplies are mixed-sign
01 = DSP engine multiplies are unsigned
00 = DSP engine multiplies are signed
EDT: Early DO Loop Termination Control bit^(1,2)
1 = Terminates executing DO loop at end of current loop iteration
0 = No effect
DL<2:0>: DO Loop Nesting Level Status bits⁽¹⁾
111 = 7 DO loops are active
•
•
•
001 = 1 DO loop is active
000 = 0 DO loops are active
SATA: ACCA Saturation Enable bit⁽¹⁾
1 = Accumulator A saturation is enabled
0 = Accumulator A saturation is disabled
SATB: ACCB Saturation Enable bit⁽¹⁾
1 = Accumulator B saturation is enabled
0 = Accumulator B saturation is disabled
SATDW: Data Space Write from DSP Engine Saturation Enable bit⁽¹⁾
1 = Data space write saturation is enabled
0 = Data space write saturation is disabled
ACCSAT: Accumulator Saturation Mode Select bit⁽¹⁾
1 = 9.31 saturation (super saturation)
0 = 1.31 saturation (normal saturation)
IPL3: CPU Interrupt Priority Level Status bit 3⁽³⁾
1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less
Note 1:
2:
3:
This bit is available on dsPIC33EPXXX(GP/MC/MU)806/810/814 devices only.
This bit is always read as ‘0’.
The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
DS70616G-page 44
 2009-2012 Microchip Technology Inc.