PIC24EP256GU810-I Datasheet, PDF (180/622 Pages) Electronic Film Capacitors, Inc. – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced Analog

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
Figure 9-3 illustrates a block diagram of the auxiliary
PLL module.
Note:
The auxiliary PLL module is only avail-
able on dsPIC33EPXXXMU8XX and
PIC24EPXXXGU8XX devices.
FIGURE 9-3:
APLL BLOCK DIAGRAM
3 MHz < FAREF < 5.5 MHz
FAIN
÷ N1
FAREF
PFD
APLLPRE<2:0>
60 MHZ < FAVCO < 120 MHZ
VCO
FAVCO
÷M
APLLDIV<2:0>
Equation 9-4 shows the relationship between the
auxiliary PLL input clock frequency (FAIN) and the
AVCO frequency (FAVCO).
EQUATION 9-4: FAVCO CALCULATION
FAVCO
=
F
AI
N



N^{--M---1-}
DS70616G-page 180
 2009-2012 Microchip Technology Inc.