PIC24EP256GU810-I Datasheet, PDF (340/622 Pages) Electronic Film Capacitors, Inc. – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced Analog

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
REGISTER 18-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED)
bit 1
SPITBF: SPIx Transmit Buffer Full Status bit
1 = Transmit has not yet started, SPIx transmit buffer is full
0 = Transmit has started, SPIx transmit buffer is empty
Standard Buffer Mode:
Automatically set in hardware when the core writes to the SPIxBUF location, loading the SPIx transmit
buffer. Automatically cleared in hardware when the SPIx module transfers data from the SPIx transmit
buffer to SPIxSR.
Enhanced Buffer Mode:
Automatically set in hardware when CPU writes to the SPIxBUF location, loading the last available
buffer location. Automatically cleared in hardware when a buffer location is available for a CPU write
operation.
bit 0
SPIRBF: SPIx Receive Buffer Full Status bit
1 = Receive complete, SPIx receive buffer is full
0 = Receive is incomplete, SPIx receive buffer is empty
Standard Buffer Mode:
Automatically set in hardware when SPIx transfers data from SPIxSR to the SPIx receive buffer.
Automatically cleared in hardware when the core reads the SPIxBUF location, reading the SPIx
receive buffer.
Enhanced Buffer Mode:
Automatically set in hardware when SPIx transfers data from SPIxSR to the buffer, filling the last
unread buffer location. Automatically cleared in hardware when a buffer location is available for a
transfer from SPIxSR.
DS70616G-page 340
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