PIC24EP256GU810-I Datasheet, PDF(306/622 Page) Electronic Film Capacitors, Inc. – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced Analog

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PIC24EP256GU810-I Datasheet, PDF (306/622 Pages) Electronic Film Capacitors, Inc. – 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, USB and Advanced Analog

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dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814

REGISTER 16-11: PWMCONx: PWMx CONTROL REGISTER (CONTINUED)

bit 7-6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

DTC<1:0>: Dead-Time Control bits

11 = Dead-Time Compensation mode

10 = Dead-time function is disabled

01 = Negative dead time actively applied for Complementary Output mode

00 = Positive dead time actively applied for all output modes

DTCP: Dead-Time Compensation Polarity bit(3)

When set to â1â:

If DTCMPx = 0, PWMxL is shortened and PWMxH is lengthened.

If DTCMPx = 1, PWMxH is shortened and PWMxL is lengthened.

When set to â0â:

If DTCMPx = 0, PWMxH is shortened and PWMxL is lengthened.

If DTCMPx = 1, PWMxL is shortened and PWMxH is lengthened.

Unimplemented: Read as â0â

MTBS: Master Time Base Select bit

1 = PWM generator uses the secondary master time base for synchronization and as the clock source

for the PWM generation logic (if secondary time base is available)

0 = PWM generator uses the primary master time base for synchronization and as the clock source

for the PWM generation logic

CAM: Center-Aligned Mode Enable bit(2,4)

1 = Center-Aligned mode is enabled

0 = Edge-Aligned mode is enabled

XPRES: External PWM Reset Control bit(5)

1 = Current-limit source resets the time base for this PWM generator if it is in Independent Time Base

mode

0 = External pins do not affect PWM time base

IUE: Immediate Update Enable bit(2)

1 = Updates to the active MDC/PDCx/SDCx registers are immediate

0 = Updates to the active PDCx registers are synchronized to the PWM time base

Note 1:

2:

3:

4:

5:

Software must clear the interrupt status here and in the corresponding IFS bit in the interrupt controller.

These bits should not be changed after the PWM is enabled (PTEN = 1).

DTC<1:0> = 11 for DTCP to be effective; otherwise, DTCP is ignored.

The Independent Time Base (ITB = 1) mode must be enabled to use Center-Aligned mode. If ITB = 0, the

CAM bit is ignored.

To operate in External Period Reset mode, the ITB bit must be â1â and the CLMOD bit in the FCLCONx

register must be â0â.

DS70616G-page 306

ï£ 2009-2012 Microchip Technology Inc.

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